diff mbox series

[U-Boot,v2,9/9] ARM: dts: rk322x: Correct the uart2 default pin configuration

Message ID 20190102130235.26442-1-david.wu@rock-chips.com
State Accepted
Delegated to: Philipp Tomsich
Headers show
Series Add common pinctrl driver support for rockchip | expand

Commit Message

David Wu Jan. 2, 2019, 1:02 p.m. UTC
To match the iomux setting of uart2 at SPL, correct the uart2
default pin configuration, if not changed, the evb-rk3229 can't
output the log message.

Signed-off-by: David Wu <david.wu@rock-chips.com>
---

Changes in v2: None

 arch/arm/dts/rk322x.dtsi | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

Comments

Kever Yang Jan. 22, 2019, 9:16 a.m. UTC | #1
On 01/02/2019 09:02 PM, David Wu wrote:
> To match the iomux setting of uart2 at SPL, correct the uart2
> default pin configuration, if not changed, the evb-rk3229 can't
> output the log message.
>
> Signed-off-by: David Wu <david.wu@rock-chips.com>

Reviewed-by: Kever Yang <kever.yang@rock-chips.com>

Thanks,
- Kever
> ---
>
> Changes in v2: None
>
>  arch/arm/dts/rk322x.dtsi | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
> index be026b0e07..4a8be5dabb 100644
> --- a/arch/arm/dts/rk322x.dtsi
> +++ b/arch/arm/dts/rk322x.dtsi
> @@ -206,7 +206,7 @@
>  		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
>  		clock-names = "baudclk", "apb_pclk";
>  		pinctrl-names = "default";
> -		pinctrl-0 = <&uart2_xfer>;
> +		pinctrl-0 = <&uart21_xfer>;
>  		reg-shift = <2>;
>  		reg-io-width = <4>;
>  		status = "disabled";
> @@ -748,7 +748,7 @@
>  
>  		uart2 {
>  			uart2_xfer: uart2-xfer {
> -				rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
> +				rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_up>,
>  						<1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
>  			};
>  
> @@ -760,6 +760,13 @@
>  				rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
>  			};
>  		};
> +
> +		uart2-1 {
> +			uart21_xfer: uart21-xfer {
> +				rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
> +						<1 9 RK_FUNC_2 &pcfg_pull_none>;
> +			};
> +		};
>  	};
>  
>  	dmc: dmc@11200000 {
Philipp Tomsich Jan. 31, 2019, 10:15 a.m. UTC | #2
> To match the iomux setting of uart2 at SPL, correct the uart2
> default pin configuration, if not changed, the evb-rk3229 can't
> output the log message.
> 
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
> Changes in v2: None
> 
>  arch/arm/dts/rk322x.dtsi | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 

Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich Jan. 31, 2019, 9:12 p.m. UTC | #3
> To match the iomux setting of uart2 at SPL, correct the uart2
> default pin configuration, if not changed, the evb-rk3229 can't
> output the log message.
> 
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
> Changes in v2: None
> 
>  arch/arm/dts/rk322x.dtsi | 11 +++++++++--
>  1 file changed, 9 insertions(+), 2 deletions(-)
> 

Applied to u-boot-rockchip, thanks!
diff mbox series

Patch

diff --git a/arch/arm/dts/rk322x.dtsi b/arch/arm/dts/rk322x.dtsi
index be026b0e07..4a8be5dabb 100644
--- a/arch/arm/dts/rk322x.dtsi
+++ b/arch/arm/dts/rk322x.dtsi
@@ -206,7 +206,7 @@ 
 		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 		clock-names = "baudclk", "apb_pclk";
 		pinctrl-names = "default";
-		pinctrl-0 = <&uart2_xfer>;
+		pinctrl-0 = <&uart21_xfer>;
 		reg-shift = <2>;
 		reg-io-width = <4>;
 		status = "disabled";
@@ -748,7 +748,7 @@ 
 
 		uart2 {
 			uart2_xfer: uart2-xfer {
-				rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
+				rockchip,pins = <1 RK_PC2 RK_FUNC_2 &pcfg_pull_up>,
 						<1 RK_PC3 RK_FUNC_2 &pcfg_pull_none>;
 			};
 
@@ -760,6 +760,13 @@ 
 				rockchip,pins = <0 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
 			};
 		};
+
+		uart2-1 {
+			uart21_xfer: uart21-xfer {
+				rockchip,pins = <1 10 RK_FUNC_2 &pcfg_pull_up>,
+						<1 9 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
 	};
 
 	dmc: dmc@11200000 {