diff mbox series

[U-Boot,v1] ARM: vf610: ddrmc: program Dummy DDRBYTE1/2

Message ID 20181214142600.27189-1-stefan@agner.ch
State Accepted
Commit a95d444055134fd8f0e1f2bd4c11222170fe6dc5
Delegated to: Stefano Babic
Headers show
Series [U-Boot,v1] ARM: vf610: ddrmc: program Dummy DDRBYTE1/2 | expand

Commit Message

Stefan Agner Dec. 14, 2018, 2:26 p.m. UTC 
From: Stefan Agner <stefan.agner@toradex.com>

The Vybrid reference manual VFXXXRM Rev. 0 10/2016 states in chapter
5.2.6.1 DUMMY PADS (DDR/QuadSPI) that those pads need to be programed
for correct operation of DDR. Assume the default DDR pin configuration
which seems to work well on a Colibri VF50.

Signed-off-by: Stefan Agner <stefan.agner@toradex.com>
---

 arch/arm/include/asm/arch-vf610/iomux-vf610.h | 2 ++
 arch/arm/mach-imx/ddrmc-vf610.c               | 2 ++
 2 files changed, 4 insertions(+)
diff mbox series

Patch

diff --git a/arch/arm/include/asm/arch-vf610/iomux-vf610.h b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
index c0eeaa7e7d..01bc2998b8 100644
--- a/arch/arm/include/asm/arch-vf610/iomux-vf610.h
+++ b/arch/arm/include/asm/arch-vf610/iomux-vf610.h
@@ -244,6 +244,8 @@  enum {
 	VF610_PAD_DDR_WE__DDR_WE_B		= IOMUX_PAD(0x02d0, 0x02d0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_ODT1__DDR_ODT_0		= IOMUX_PAD(0x02d4, 0x02d4, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 	VF610_PAD_DDR_ODT0__DDR_ODT_1		= IOMUX_PAD(0x02d8, 0x02d8, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1	= IOMUX_PAD(0x02dc, 0x02dc, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
+	VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2	= IOMUX_PAD(0x02e0, 0x02e0, 0, __NA_, 0, VF610_DDR_PAD_CTRL),
 };
 
 #endif	/* __IOMUX_VF610_H__ */
diff --git a/arch/arm/mach-imx/ddrmc-vf610.c b/arch/arm/mach-imx/ddrmc-vf610.c
index 3d7da1c25e..7cc8f5d2c0 100644
--- a/arch/arm/mach-imx/ddrmc-vf610.c
+++ b/arch/arm/mach-imx/ddrmc-vf610.c
@@ -61,6 +61,8 @@  void ddrmc_setup_iomux(const iomux_v3_cfg_t *pads, int pads_count)
 		VF610_PAD_DDR_WE__DDR_WE_B,
 		VF610_PAD_DDR_ODT1__DDR_ODT_0,
 		VF610_PAD_DDR_ODT0__DDR_ODT_1,
+		VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1,
+		VF610_PAD_DDR_DDRBYTE2__DDR_DDRBYTE2,
 		VF610_PAD_DDR_RESETB,
 	};