From patchwork Tue Dec 4 12:26:51 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vignesh Raghavendra X-Patchwork-Id: 1007590 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="g/beiExu"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 438LjT3r01z9s7W for ; Tue, 4 Dec 2018 23:27:41 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id F1945C221FA; Tue, 4 Dec 2018 12:27:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 72B7DC2222B; Tue, 4 Dec 2018 12:27:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E9DB5C2231A; Tue, 4 Dec 2018 12:26:53 +0000 (UTC) Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lists.denx.de (Postfix) with ESMTPS id 46935C22206 for ; Tue, 4 Dec 2018 12:26:49 +0000 (UTC) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id wB4CQiVa082756; Tue, 4 Dec 2018 06:26:44 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1543926404; bh=x/CEImJ1yvVYou8uvw3GU+PObBySrZHKASSAmqjs6QM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=g/beiExuPxwrz4XT+QKc+b8EFcyt3bmXsI8AWEolZWLpzFqRrZEw6IhzN5LDqc1gy C42GbRPUfYwOFOt2ls4A8O28FaTTDgUDxlDgDfb9BX0Wsl/bYOILb6BG3Esh5TMQZn A8otuNeeCjW15xxzLmSBTsXy3pybIG6vQjpqezkM= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id wB4CQi6w077404 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 4 Dec 2018 06:26:44 -0600 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Tue, 4 Dec 2018 06:26:44 -0600 Received: from dlep32.itg.ti.com (157.170.170.100) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1591.10 via Frontend Transport; Tue, 4 Dec 2018 06:26:44 -0600 Received: from a0132425.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id wB4CQMWb017678; Tue, 4 Dec 2018 06:26:39 -0600 From: Vignesh R To: Nobuhiro Iwamatsu , Heiko Schocher , Jagan Teki , Patrick Delaunay , Christophe Kerello , Patrice Chotard Date: Tue, 4 Dec 2018 17:56:51 +0530 Message-ID: <20181204122659.14720-4-vigneshr@ti.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181204122659.14720-1-vigneshr@ti.com> References: <20181204122659.14720-1-vigneshr@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tom Rini , u-boot@lists.denx.de, uboot-stm32@st-md-mailman.stormreply.com, Miquel Raynal , Fabio Estevam , Boris Brezillon Subject: [U-Boot] [RFC PATCH v2 03/11] spi: Add non DM version of SPI_MEM X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add non DM version of SPI_MEM to support easy migration to new SPI NOR framework. This can be removed once DM_SPI conversion is complete. Signed-off-by: Vignesh R --- drivers/spi/Kconfig | 4 +- drivers/spi/Makefile | 1 + drivers/spi/spi-mem-nodm.c | 89 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 92 insertions(+), 2 deletions(-) create mode 100644 drivers/spi/spi-mem-nodm.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 516188ea88e1..de334a33a283 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -16,8 +16,6 @@ config DM_SPI typically use driver-private data instead of extending the spi_slave structure. -if DM_SPI - config SPI_MEM bool "SPI memory extension" help @@ -25,6 +23,8 @@ config SPI_MEM This extension is meant to simplify interaction with SPI memories by providing an high-level interface to send memory-like commands. +if DM_SPI + config ALTERA_SPI bool "Altera SPI driver" help diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 7242ea7e4045..66666b26133f 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_SOFT_SPI) += soft_spi.o obj-$(CONFIG_SPI_MEM) += spi-mem.o else obj-y += spi.o +obj-$(CONFIG_SPI_MEM) += spi-mem-nodm.o obj-$(CONFIG_SOFT_SPI) += soft_spi_legacy.o endif diff --git a/drivers/spi/spi-mem-nodm.c b/drivers/spi/spi-mem-nodm.c new file mode 100644 index 000000000000..4d91761f56d3 --- /dev/null +++ b/drivers/spi/spi-mem-nodm.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +#include +#include + +int spi_mem_exec_op(struct spi_slave *slave, + const struct spi_mem_op *op) +{ + unsigned int pos = 0; + const u8 *tx_buf = NULL; + u8 *rx_buf = NULL; + u8 *op_buf; + int op_len; + u32 flag; + int ret; + int i; + + if (op->data.nbytes) { + if (op->data.dir == SPI_MEM_DATA_IN) + rx_buf = op->data.buf.in; + else + tx_buf = op->data.buf.out; + } + + op_len = sizeof(op->cmd.opcode) + op->addr.nbytes + op->dummy.nbytes; + op_buf = calloc(1, op_len); + + ret = spi_claim_bus(slave); + if (ret < 0) + return ret; + + op_buf[pos++] = op->cmd.opcode; + + if (op->addr.nbytes) { + for (i = 0; i < op->addr.nbytes; i++) + op_buf[pos + i] = op->addr.val >> + (8 * (op->addr.nbytes - i - 1)); + + pos += op->addr.nbytes; + } + + if (op->dummy.nbytes) + memset(op_buf + pos, 0xff, op->dummy.nbytes); + + /* 1st transfer: opcode + address + dummy cycles */ + flag = SPI_XFER_BEGIN; + /* Make sure to set END bit if no tx or rx data messages follow */ + if (!tx_buf && !rx_buf) + flag |= SPI_XFER_END; + + ret = spi_xfer(slave, op_len * 8, op_buf, NULL, flag); + if (ret) + return ret; + + /* 2nd transfer: rx or tx data path */ + if (tx_buf || rx_buf) { + ret = spi_xfer(slave, op->data.nbytes * 8, tx_buf, + rx_buf, SPI_XFER_END); + if (ret) + return ret; + } + + spi_release_bus(slave); + + for (i = 0; i < pos; i++) + debug("%02x ", op_buf[i]); + debug("| [%dB %s] ", + tx_buf || rx_buf ? op->data.nbytes : 0, + tx_buf || rx_buf ? (tx_buf ? "out" : "in") : "-"); + for (i = 0; i < op->data.nbytes; i++) + debug("%02x ", tx_buf ? tx_buf[i] : rx_buf[i]); + debug("[ret %d]\n", ret); + + free(op_buf); + + if (ret < 0) + return ret; + + return 0; +} + +int spi_mem_adjust_op_size(struct spi_slave *slave, + struct spi_mem_op *op) +{ + return 0; +}