Message ID | 20181202204222.30732-2-lukma@denx.de |
---|---|
State | Superseded |
Delegated to: | Stefano Babic |
Headers | show |
Series | ddr: vybrid: Support for vf610 built-in DDR3 memory calibration | expand |
On 02.12.2018 21:42, Lukasz Majewski wrote: > This commit provides extra defines needed for DDR memory controller > calibration (read leveling performing). > > Signed-off-by: Lukasz Majewski <lukma@denx.de> > --- > > arch/arm/include/asm/arch-vf610/imx-regs.h | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h > b/arch/arm/include/asm/arch-vf610/imx-regs.h > index 08ba8e94f8..f477e414f9 100644 > --- a/arch/arm/include/asm/arch-vf610/imx-regs.h > +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h > @@ -206,11 +206,17 @@ > #define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16) > #define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf) > #define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16) > +#define DDRMC_CR93_SW_LVL_MODE(v) (((v) & 0x3) << 8) > +#define DDRMC_CR93_SWLVL_LOAD BIT(16) > +#define DDRMC_CR93_SWLVL_START BIT(24) > +#define DDRMC_CR93_SWLVL_EXIT BIT(0) SWLVL_EXIT is in CR94. With that fixed, looks good. Reviewed-by: Stefan Agner <stefan.agner@toradex.com> -- Stefan > +#define DDRMC_CR94_SWLVL_OP_DONE BIT(8) > #define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) > #define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) > #define DDRMC_CR97_WRLVL_EN (1 << 24) > #define DDRMC_CR98_WRLVL_DL_0(v) ((v) & 0xffff) > #define DDRMC_CR99_WRLVL_DL_1(v) ((v) & 0xffff) > +#define DDRMC_CR101_PHY_RDLVL_EDGE BIT(24) > #define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16) > #define DDRMC_CR102_RDLVL_REG_EN (1 << 8) > #define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8)
diff --git a/arch/arm/include/asm/arch-vf610/imx-regs.h b/arch/arm/include/asm/arch-vf610/imx-regs.h index 08ba8e94f8..f477e414f9 100644 --- a/arch/arm/include/asm/arch-vf610/imx-regs.h +++ b/arch/arm/include/asm/arch-vf610/imx-regs.h @@ -206,11 +206,17 @@ #define DDRMC_CR88_TODTL_CMD(v) (((v) & 0x1f) << 16) #define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf) #define DDRMC_CR91_R2W_SMCSDL(v) (((v) & 0x7) << 16) +#define DDRMC_CR93_SW_LVL_MODE(v) (((v) & 0x3) << 8) +#define DDRMC_CR93_SWLVL_LOAD BIT(16) +#define DDRMC_CR93_SWLVL_START BIT(24) +#define DDRMC_CR93_SWLVL_EXIT BIT(0) +#define DDRMC_CR94_SWLVL_OP_DONE BIT(8) #define DDRMC_CR96_WLMRD(v) (((v) & 0x3f) << 8) #define DDRMC_CR96_WLDQSEN(v) ((v) & 0x3f) #define DDRMC_CR97_WRLVL_EN (1 << 24) #define DDRMC_CR98_WRLVL_DL_0(v) ((v) & 0xffff) #define DDRMC_CR99_WRLVL_DL_1(v) ((v) & 0xffff) +#define DDRMC_CR101_PHY_RDLVL_EDGE BIT(24) #define DDRMC_CR102_RDLVL_GT_REGEN (1 << 16) #define DDRMC_CR102_RDLVL_REG_EN (1 << 8) #define DDRMC_CR105_RDLVL_DL_0(v) (((v) & 0xff) << 8)
This commit provides extra defines needed for DDR memory controller calibration (read leveling performing). Signed-off-by: Lukasz Majewski <lukma@denx.de> --- arch/arm/include/asm/arch-vf610/imx-regs.h | 6 ++++++ 1 file changed, 6 insertions(+)