From patchwork Wed Nov 21 03:41:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 1000905 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=brainfault.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=brainfault-org.20150623.gappssmtp.com header.i=@brainfault-org.20150623.gappssmtp.com header.b="Ypr5pPMH"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4307hf59b8z9s0n for ; Wed, 21 Nov 2018 14:43:30 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 6A27DC221BD; Wed, 21 Nov 2018 03:42:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.6 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, RCVD_IN_SORBS_WEB, T_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6FBFCC22202; Wed, 21 Nov 2018 03:42:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C1A23C221BD; Wed, 21 Nov 2018 03:41:40 +0000 (UTC) Received: from mail-pl1-f194.google.com (mail-pl1-f194.google.com [209.85.214.194]) by lists.denx.de (Postfix) with ESMTPS id 5ED4CC221D0 for ; Wed, 21 Nov 2018 03:41:37 +0000 (UTC) Received: by mail-pl1-f194.google.com with SMTP id b22-v6so3386003pls.7 for ; Tue, 20 Nov 2018 19:41:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=brainfault-org.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=u7TpTYu8xrrnenTnTzxQh6fp0tbd1VldV3TZ352yTKc=; b=Ypr5pPMH32STgS6i13h3mIgRir5aJDuhPK3QmHocw+6Xe6R8lS76qPBkwEiJDH/kWf B1PUbpw5lOjfcBsiVVC8iIHl3FOtyFUjjrQagh93DjvYU2B9YHf2YPMb2ppkr41Cdw62 NfJhGFoQ7nShdzVdotExM+q2+WB99LwtKX47Px3D4eKMtE+WF3eyE/p4xFs3sznWweBG jBZsNQAfrBGEcZcuXbuHi5GyIbRK3nZNfxMtlSUuX8aqJ3fYMV76avEX7XET+kcF6pvR UWLZoxI64v6Y2W8SZPvJojnx5EywXSmKUWBXglPASjNrlaxbh3BcWukfRFj0XEJQlFHs l5/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=u7TpTYu8xrrnenTnTzxQh6fp0tbd1VldV3TZ352yTKc=; b=OuyLqkVrwvzTyJyXjz17xCSERGYeSnz+CEpMifwmdgkY22ZegqBFlhC5pdOtjNLYMz 0qfkKkJsc7+tSKSKciTzQymJIFY8uunDm9ut2EnBPyufGP7P54geYaskz885M5H8B0yO 0jKrXZRM7pMezF4dKaLEVHkAdhuKkFuy55Mkuc/V0QhxnjECBpvPvUFzuPx5AY3CADyd HkPgRhBDy2bIUhopG0MwTzPJIWwUgWH/8Ii1b3oPu5ENW6ttFqEzj+E4nA0ax3/PLO/y paVASVid7yIAcArggV4L4mB0mLDYJHSejKne7D1tCo9Bs2Fk4jiJ/wOEVNTlMEWv/Ov/ RxbQ== X-Gm-Message-State: AGRZ1gKsJx5eUizd0qgQGYfqv7j/U0QGW8AIggkmrh5mftQHzsfEjhw/ sGgY7HCUm7d/kBp1BSwj3IlNtg== X-Google-Smtp-Source: AJdET5c2xcXaeq2ugBWb6wLoY0kzMbpJ96q5KsE+gE9qP1GCXF9VONBpaQE1ZJXJFvaeTm2n/RHEEw== X-Received: by 2002:a62:7c47:: with SMTP id x68mr4389008pfc.209.1542771695773; Tue, 20 Nov 2018 19:41:35 -0800 (PST) Received: from localhost.localdomain ([106.51.20.239]) by smtp.googlemail.com with ESMTPSA id b185sm53870623pga.85.2018.11.20.19.41.32 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 20 Nov 2018 19:41:35 -0800 (PST) From: Anup Patel To: Rick Chen Date: Wed, 21 Nov 2018 09:11:11 +0530 Message-Id: <20181121034112.7136-3-anup@brainfault.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181121034112.7136-1-anup@brainfault.org> References: <20181121034112.7136-1-anup@brainfault.org> Cc: U-Boot Mailing List , Palmer Dabbelt , Alexander Graf , Christoph Hellwig , Atish Patra Subject: [U-Boot] [PATCH v3 2/3] riscv: qemu: Use different SYS_TEXT_BASE for S-mode X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" When u-boot runs in S-mode, the M-mode runtime firmware (BBL or equivalent) uses memory range in 0x80000000 to 0x80200000. Due to this, we cannot use 0x80000000 as SYS_TEXT_BASE when running in S-mode. Instead for S-mode, we use 0x80200000 as SYS_TEXT_BASE. Even Linux RISC-V kernel ignores/reserves memory range 0x80000000 to 0x80200000 because it runs in S-mode. Signed-off-by: Anup Patel Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Lukas Auer --- board/emulation/qemu-riscv/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig index 33ca253432..56bb5337d4 100644 --- a/board/emulation/qemu-riscv/Kconfig +++ b/board/emulation/qemu-riscv/Kconfig @@ -13,7 +13,8 @@ config SYS_CONFIG_NAME default "qemu-riscv" config SYS_TEXT_BASE - default 0x80000000 + default 0x80000000 if !RISCV_SMODE + default 0x80200000 if RISCV_SMODE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y