From patchwork Thu Oct 18 12:28:18 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anatolij Gustschin X-Patchwork-Id: 985865 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=denx.de Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42bTNn2Vbcz9s89 for ; Thu, 18 Oct 2018 23:48:09 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E4A5DC21E0B; Thu, 18 Oct 2018 12:37:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id EDBB1C21ED5; Thu, 18 Oct 2018 12:29:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 6984BC21EA7; Thu, 18 Oct 2018 12:29:13 +0000 (UTC) Received: from mail-out.m-online.net (mail-out.m-online.net [212.18.0.10]) by lists.denx.de (Postfix) with ESMTPS id 4D6D7C21E36 for ; Thu, 18 Oct 2018 12:29:05 +0000 (UTC) Received: from frontend01.mail.m-online.net (unknown [192.168.8.182]) by mail-out.m-online.net (Postfix) with ESMTP id 42bSyn0zWlz1qxDK; Thu, 18 Oct 2018 14:29:05 +0200 (CEST) Received: from localhost (dynscan1.mnet-online.de [192.168.6.70]) by mail.m-online.net (Postfix) with ESMTP id 42bSyn0jhNz1qqkH; Thu, 18 Oct 2018 14:29:05 +0200 (CEST) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.8.182]) by localhost (dynscan1.mail.m-online.net [192.168.6.70]) (amavisd-new, port 10024) with ESMTP id 5u32oIgxz6sw; Thu, 18 Oct 2018 14:29:04 +0200 (CEST) X-Auth-Info: KZh32Vnfft2Fa9lXzpjhCJIR7Rpjq9iso0pAkt7b3Vw= Received: from crub.agik.hopto.org (p508DEB69.dip0.t-ipconnect.de [80.141.235.105]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.mnet-online.de (Postfix) with ESMTPSA; Thu, 18 Oct 2018 14:29:04 +0200 (CEST) From: Anatolij Gustschin To: u-boot@lists.denx.de, peng.fan@nxp.com, sbabic@denx.de Date: Thu, 18 Oct 2018 14:28:18 +0200 Message-Id: <20181018122837.31582-16-agust@denx.de> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20181018122837.31582-1-agust@denx.de> References: <20181018122837.31582-1-agust@denx.de> Subject: [U-Boot] [PATCH v6 15/34] imx8: add basic cpu support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Peng Fan Add basic cpu support, including cpu revision, cpu type, cpu core detection. Signed-off-by: Peng Fan Reviewed-by: Anatolij Gustschin Cc: Stefano Babic --- arch/arm/mach-imx/imx8/Makefile | 7 +++ arch/arm/mach-imx/imx8/cpu.c | 93 +++++++++++++++++++++++++++++++++ 2 files changed, 100 insertions(+) create mode 100644 arch/arm/mach-imx/imx8/Makefile create mode 100644 arch/arm/mach-imx/imx8/cpu.c diff --git a/arch/arm/mach-imx/imx8/Makefile b/arch/arm/mach-imx/imx8/Makefile new file mode 100644 index 0000000000..57876139a1 --- /dev/null +++ b/arch/arm/mach-imx/imx8/Makefile @@ -0,0 +1,7 @@ +# +# Copyright 2018 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += cpu.o diff --git a/arch/arm/mach-imx/imx8/cpu.c b/arch/arm/mach-imx/imx8/cpu.c new file mode 100644 index 0000000000..0b841e291d --- /dev/null +++ b/arch/arm/mach-imx/imx8/cpu.c @@ -0,0 +1,93 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +u32 get_cpu_rev(void) +{ + u32 id = 0, rev = 0; + int ret; + + ret = sc_misc_get_control(-1, SC_R_SYSTEM, SC_C_ID, &id); + if (ret) + return 0; + + rev = (id >> 5) & 0xf; + id = (id & 0x1f) + MXC_SOC_IMX8; /* Dummy ID for chip */ + + return (id << 12) | rev; +} + +#ifdef CONFIG_DISPLAY_CPUINFO +const char *get_imx8_type(u32 imxtype) +{ + switch (imxtype) { + case MXC_CPU_IMX8QXP: + return "8QXP"; + default: + return "??"; + } +} + +const char *get_imx8_rev(u32 rev) +{ + switch (rev) { + case CHIP_REV_A: + return "A"; + case CHIP_REV_B: + return "B"; + default: + return "?"; + } +} + +const char *get_core_name(void) +{ + if (is_cortex_a35()) + return "A35"; + else + return "?"; +} + +int print_cpuinfo(void) +{ + struct udevice *dev; + struct clk cpu_clk; + int ret; + + ret = uclass_get_device(UCLASS_CPU, 0, &dev); + if (ret) + return 0; + + ret = clk_get_by_index(dev, 0, &cpu_clk); + if (ret) { + dev_err(dev, "failed to clk\n"); + return 0; + } + + u32 cpurev; + + cpurev = get_cpu_rev(); + + printf("CPU: Freescale i.MX%s rev%s %s at %ld MHz\n", + get_imx8_type((cpurev & 0xFF000) >> 12), + get_imx8_rev((cpurev & 0xFFF)), + get_core_name(), + clk_get_rate(&cpu_clk) / 1000000); + + return 0; +} +#endif