From patchwork Fri Sep 7 17:18:44 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Schwierzeck X-Patchwork-Id: 967436 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ZtOQ38SC"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 426PLM439pz9s3Z for ; Sat, 8 Sep 2018 03:19:02 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id E3049C21DD9; Fri, 7 Sep 2018 17:18:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5BF87C21D4A; Fri, 7 Sep 2018 17:18:52 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A88EBC21D4A; Fri, 7 Sep 2018 17:18:50 +0000 (UTC) Received: from mail-wm0-f68.google.com (mail-wm0-f68.google.com [74.125.82.68]) by lists.denx.de (Postfix) with ESMTPS id 53168C21C2F for ; Fri, 7 Sep 2018 17:18:50 +0000 (UTC) Received: by mail-wm0-f68.google.com with SMTP id j192-v6so15420053wmj.1 for ; Fri, 07 Sep 2018 10:18:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=a5uvAVro0m0+4WGaWxOuuC/7epLzkoY6I2QcRh863Tc=; b=ZtOQ38SC+Hzu0dykaA875pgnEgRih8BUmBJNsIwx3lqGlNF9Phoj2MYyMlmE+87RVz O4Fg4lvuXiZ3nUS/gHkvyFthpO3GXGLJsV8T1am9V2G12hkVeQvHxBJQiLwRh+1pBnF2 CIl7194aQX38PgU/BPiBIri9HcvJ753qSbwnI+fuy+EbwVAoqrU4jqs43Y6a+cikrfKF 8sfnTY7AT643yp2Joy+Eqaal4kR3/BgLdZPvo1YGiXLasadQkO76gSUb1Fxaw1NRx0+0 wIwfRw/Y6sSAWpkSu1hNO62q/nSl+KBtyjQnlEpLwpcTd95eTSWVig73Rignzm4Jwgza eugQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=a5uvAVro0m0+4WGaWxOuuC/7epLzkoY6I2QcRh863Tc=; b=PLxB6utZzFZSCk7nfofgPC0eZXlDZZ4p+Jn6kFzKY4FrLO0mQsM8c2tlPXOxX0On3o 408xSZBbhH1o14HneJgWXhDA2deSgfGKYNHPKO+UNMNbbmBySfFPsWGb5scnioKJaUl8 oweI3A0f16Zt+TTrVNzGeZhlu6EODoIc1vyVqsDU6FD47LZ72grqS8900j0/BF4B2o/S l3c5fwd5USY1OrtAUO5OUgKbXPgrIR6n0wcVeq6x60YYqUWFYqoPNNIjN8Y+Vsh2e2lo WSSOFFwwH7se366NRhGEX0RlA9qUxEJLpJudWe1uFzdaHHz/rZE2Jz8ryB686tC7YPhJ FpFA== X-Gm-Message-State: APzg51AaO0LV3GJ1mXq9bjBcVsHwgkmB5uAcUAJ7nuhJBTSKB73ROmD3 l/BGg+m7HLKR6yeje13ebUVkWQ49 X-Google-Smtp-Source: ANB0VdZB+/7kc+GxSHqdd9Ih0I9fvsnP46m65+sOir6geF1/qPqJsbwgmOgmjiez8GmIgI7tLViQQA== X-Received: by 2002:a1c:ba84:: with SMTP id k126-v6mr5521863wmf.96.1536340729666; Fri, 07 Sep 2018 10:18:49 -0700 (PDT) Received: from workstation.lan.schwierd.dedyn.io (p549C7405.dip0.t-ipconnect.de. [84.156.116.5]) by smtp.gmail.com with ESMTPSA id g17-v6sm6803246wmh.19.2018.09.07.10.18.48 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 07 Sep 2018 10:18:48 -0700 (PDT) From: Daniel Schwierzeck To: u-boot@lists.denx.de Date: Fri, 7 Sep 2018 19:18:44 +0200 Message-Id: <20180907171844.19185-1-daniel.schwierzeck@gmail.com> X-Mailer: git-send-email 2.18.0 Subject: [U-Boot] [PATCH] MIPS: start.S: make boot config at offset 0x10 configurable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Some MIPS systems store some board-specific boot configuration in the U-Boot binary at offset 0x10. This is used by Malta boards and by Lantiq/Intel SoC's when booting from parallel NOR flash. Convert the hard-coded values to Kconfig options to remove such board-specific stuff out of the generic start.S code. This also deprecates the config option CONFIG_SYS_XWAY_EBU_BOOTCFG. Signed-off-by: Daniel Schwierzeck --- README | 5 ----- arch/mips/Kconfig | 22 ++++++++++++++++++++++ arch/mips/cpu/start.S | 21 +++++---------------- scripts/config_whitelist.txt | 1 - 4 files changed, 27 insertions(+), 22 deletions(-) diff --git a/README b/README index a91af2a189..0afb7779ed 100644 --- a/README +++ b/README @@ -542,11 +542,6 @@ The following options need to be configured: CONF_CM_CACHABLE_CUW CONF_CM_CACHABLE_ACCELERATED - CONFIG_SYS_XWAY_EBU_BOOTCFG - - Special option for Lantiq XWAY SoCs for booting from NOR flash. - See also arch/mips/cpu/mips32/start.S. - CONFIG_XWAY_SWAP_BYTES Enable compilation of tools/xway-swap-bytes needed for Lantiq diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 6e5e0ffe65..94da431a85 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -390,6 +390,28 @@ config MIPS_CM wish U-Boot to configure it or make use of it to retrieve system information such as cache configuration. +config MIPS_INSERT_BOOT_CONFIG + bool + default n + help + Enable this to insert some board-specific boot configuration in + the U-Boot binary at offset 0x10. + +config MIPS_BOOT_CONFIG_WORD0 + hex + depends on MIPS_INSERT_BOOT_CONFIG + default 0x420 if TARGET_MALTA + default 0x0 + help + Value which is inserted as boot config word 0. + +config MIPS_BOOT_CONFIG_WORD1 + hex + depends on MIPS_INSERT_BOOT_CONFIG + default 0x0 + help + Value which is inserted as boot config word 1. + endif endmenu diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 6ca0916c06..1d21b2324a 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -84,25 +84,14 @@ ENTRY(_start) b reset mtc0 zero, CP0_COUNT # clear cp0 count for most accurate boot timing -#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG) +#if defined(CONFIG_MIPS_INSERT_BOOT_CONFIG) /* - * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to - * access external NOR flashes. If the board boots from NOR flash the - * internal BootROM does a blind read at address 0xB0000010 to read the - * initial configuration for that EBU in order to access the flash - * device with correct parameters. This config option is board-specific. + * Store some board-specific boot configuration. This is used by some + * MIPS systems like Malta. */ .org 0x10 - .word CONFIG_SYS_XWAY_EBU_BOOTCFG - .word 0x0 -#endif -#if defined(CONFIG_MALTA) - /* - * Linux expects the Board ID here. - */ - .org 0x10 - .word 0x00000420 # 0x420 (Malta Board with CoreLV) - .word 0x00000000 + .word CONFIG_MIPS_BOOT_CONFIG_WORD0 + .word CONFIG_MIPS_BOOT_CONFIG_WORD1 #endif #if defined(CONFIG_ROM_EXCEPTION_VECTORS) diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 1a5606d123..901ab7ca54 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -4433,7 +4433,6 @@ CONFIG_SYS_XHCI_USB1_ADDR CONFIG_SYS_XHCI_USB2_ADDR CONFIG_SYS_XHCI_USB3_ADDR CONFIG_SYS_XIMG_LEN -CONFIG_SYS_XWAY_EBU_BOOTCFG CONFIG_SYS_ZYNQ_QSPI_WAIT CONFIG_SYS_ZYNQ_SPI_WAIT CONFIG_SYS_i2C_FSL