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[178.24.244.103]) by smtp.gmail.com with ESMTPSA id e141-v6sm10828362wmd.32.2018.08.26.16.16.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 26 Aug 2018 16:16:17 -0700 (PDT) From: Eugeniu Rosca X-Google-Original-From: Eugeniu Rosca To: Tom Rini , u-boot@lists.denx.de Date: Mon, 27 Aug 2018 01:13:25 +0200 Message-Id: <20180826231332.2491-8-erosca@de.adit-jv.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180826231332.2491-1-erosca@de.adit-jv.com> References: <20180826231332.2491-1-erosca@de.adit-jv.com> Cc: Eugeniu Rosca , Eugeniu Rosca Subject: [U-Boot] [PATCH v2 07/13] x86: Fix signed shift overflow in MSR_IA32_APICBASE_BASE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Fix the following UBSAN report: ====================================================================== UBSAN: Undefined behaviour in arch/x86/cpu/lapic.c:73:14 left shift of 1048575 by 12 places cannot be represented in type 'int' ====================================================================== Steps to reproduce the above: * echo CONFIG_UBSAN=y >> configs/qemu-x86_defconfig * make ARCH=x86 qemu-x86_defconfig all * qemu-system-i386 --version QEMU emulator version 2.5.0 (Debian 1:2.5+dfsg-5ubuntu10.31) * qemu-system-i386 --nographic -bios u-boot.rom Fixes: 98568f0fa96b ("x86: Import MSR/MTRR code from Linux") Signed-off-by: Eugeniu Rosca --- Changes in v2: - None. Newly pushed. --- arch/x86/include/asm/msr-index.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 9c1dbe61d596..d8b7b8013c74 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -370,7 +370,7 @@ #define MSR_IA32_APICBASE 0x0000001b #define MSR_IA32_APICBASE_BSP (1<<8) #define MSR_IA32_APICBASE_ENABLE (1<<11) -#define MSR_IA32_APICBASE_BASE (0xfffff<<12) +#define MSR_IA32_APICBASE_BASE (0xfffffUL << 12) #define MSR_IA32_TSCDEADLINE 0x000006e0