From patchwork Tue Aug 21 14:30:52 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 960421 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="Gc0SMEZf"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41vtY85Gznz9s4v for ; Wed, 22 Aug 2018 00:37:00 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 5536CC21EDE; Tue, 21 Aug 2018 14:35:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7366AC21E70; Tue, 21 Aug 2018 14:33:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C4970C21E76; Tue, 21 Aug 2018 14:32:42 +0000 (UTC) Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lists.denx.de (Postfix) with ESMTPS id 5C3A9C21E45 for ; Tue, 21 Aug 2018 14:32:36 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id w7LEWYqE115666; Tue, 21 Aug 2018 09:32:34 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1534861954; bh=/097ouMu3oUxkXd6eGBicHKS/VjOyNu/tfkqnoQWVCI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Gc0SMEZfiSytOb/QNuOEz7Fm83ZTxK8xY9hIfZm6HL1ZUPGcEzNZ+ksNGcq6pNlth 6KABbVSt5nR9+SQmduZeEU9Vc2rsg6uNpxgBSy91UlqmfRTIE/GsOqCC7Vq4DiwyMp nUJuXFV6mu54BSrKDIdfcG3K0IUm17v9r6dmkZvY= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w7LEWYLP009665; Tue, 21 Aug 2018 09:32:34 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Tue, 21 Aug 2018 09:32:34 -0500 Received: from dlep32.itg.ti.com (157.170.170.100) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Tue, 21 Aug 2018 09:32:34 -0500 Received: from uda0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dlep32.itg.ti.com (8.14.3/8.13.8) with ESMTP id w7LEWKJ6006332; Tue, 21 Aug 2018 09:32:32 -0500 From: Lokesh Vutla To: Tom Rini , Date: Tue, 21 Aug 2018 20:00:52 +0530 Message-ID: <20180821143055.29012-6-lokeshvutla@ti.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20180821143055.29012-1-lokeshvutla@ti.com> References: <20180821143055.29012-1-lokeshvutla@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tero Kristo Subject: [U-Boot] [PATCH 5/8] arm: K3: am654: Unlock control module registers during init X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Andreas Dannenberg By default the device control module registers are locked, preventing any writes to its registers. Unlock those registers as part of the init flow. Signed-off-by: Andreas Dannenberg Signed-off-by: Lokesh Vutla Reviewed-by: Tom Rini --- arch/arm/mach-k3/am6_init.c | 39 ++++++++++++++++++++ arch/arm/mach-k3/include/mach/am6_hardware.h | 21 +++++++++++ 2 files changed, 60 insertions(+) diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am6_init.c index 8a7cedf66f..d7f1dff1db 100644 --- a/arch/arm/mach-k3/am6_init.c +++ b/arch/arm/mach-k3/am6_init.c @@ -12,6 +12,42 @@ #include #ifdef CONFIG_SPL_BUILD +static void mmr_unlock(u32 base, u32 partition) +{ + /* Translate the base address */ + phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE; + + /* Unlock the requested partition if locked using two-step sequence */ + writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0); + writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1); +} + +static void ctrl_mmr_unlock(void) +{ + /* Unlock all WKUP_CTRL_MMR0 module registers */ + mmr_unlock(WKUP_CTRL_MMR0_BASE, 0); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 1); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 2); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 3); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 6); + mmr_unlock(WKUP_CTRL_MMR0_BASE, 7); + + /* Unlock all MCU_CTRL_MMR0 module registers */ + mmr_unlock(MCU_CTRL_MMR0_BASE, 0); + mmr_unlock(MCU_CTRL_MMR0_BASE, 1); + mmr_unlock(MCU_CTRL_MMR0_BASE, 2); + mmr_unlock(MCU_CTRL_MMR0_BASE, 6); + + /* Unlock all CTRL_MMR0 module registers */ + mmr_unlock(CTRL_MMR0_BASE, 0); + mmr_unlock(CTRL_MMR0_BASE, 1); + mmr_unlock(CTRL_MMR0_BASE, 2); + mmr_unlock(CTRL_MMR0_BASE, 3); + mmr_unlock(CTRL_MMR0_BASE, 6); + mmr_unlock(CTRL_MMR0_BASE, 7); + +} + static void store_boot_index_from_rom(void) { u32 *boot_index = (u32 *)K3_BOOT_PARAM_TABLE_INDEX_VAL; @@ -27,6 +63,9 @@ void board_init_f(ulong dummy) */ store_boot_index_from_rom(); + /* Make all control module registers accessible */ + ctrl_mmr_unlock(); + /* Init DM early in-order to invoke system controller */ spl_early_init(); diff --git a/arch/arm/mach-k3/include/mach/am6_hardware.h b/arch/arm/mach-k3/include/mach/am6_hardware.h index b56aa60ec7..62bc7262a3 100644 --- a/arch/arm/mach-k3/include/mach/am6_hardware.h +++ b/arch/arm/mach-k3/include/mach/am6_hardware.h @@ -17,6 +17,27 @@ #define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_MASK GENMASK(6, 4) #define CTRLMMR_MAIN_DEVSTAT_BKUP_BOOTMODE_SHIFT 4 +#define WKUP_CTRL_MMR0_BASE 0x43000000 +#define MCU_CTRL_MMR0_BASE 0x40f00000 + +/* + * The CTRL_MMR0 memory space is divided into several equally-spaced + * partitions, so defining the partition size allows us to determine + * register addresses common to those partitions. + */ +#define CTRL_MMR0_PARTITION_SIZE 0x4000 + +/* + * CTRL_MMR0, WKUP_CTRL_MMR0, and MCU_CTR_MMR0 lock/kick-mechanism + * shared register definitions. + */ +#define CTRLMMR_LOCK_KICK0 0x01008 +#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490 +#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0) +#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0 +#define CTRLMMR_LOCK_KICK1 0x0100c +#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a + /* MCU SCRATCHPAD usage */ #define K3_BOOT_PARAM_TABLE_INDEX_VAL CONFIG_MCU_SCRATCHPAD_BASE