From patchwork Mon Aug 13 07:33:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 956860 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="RijtP6DW"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41pncj25K0z9s8T for ; Mon, 13 Aug 2018 17:37:25 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id E0ED3C21DA6; Mon, 13 Aug 2018 07:36:37 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 36246C21E63; Mon, 13 Aug 2018 07:35:27 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3A1A7C21E12; Mon, 13 Aug 2018 07:34:24 +0000 (UTC) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by lists.denx.de (Postfix) with ESMTPS id 23ED7C21E0D for ; Mon, 13 Aug 2018 07:34:21 +0000 (UTC) Received: by mail-wr1-f67.google.com with SMTP id v14-v6so13346317wro.5 for ; Mon, 13 Aug 2018 00:34:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=fV7ccHviKdT5N80jdO6dd53UrhaOoJRUZfoKN6BxqsE=; b=RijtP6DWRq7GthON4+qOE240bWlNK7+RyOuifRE0rZoP+AHwO4Vs/+q6jUSq7sbDt8 HKmbHp+XIL+dL5eR5MhqKjHqkbfYnMLx8Se8/7B3LjHRYgAinK1TDL0hWNKzRPbkD7Eq Aen6XQCFhKXmP8BfSaanfSok3tVWu1omy9GQJ54iEtFs5LXaTsc3JKJJxT3sAFw2M4NB cugDYAmHhvnZs+rEJqmpE58zlIJQ35QY1noAlQdbtPNjivGQA/Yi4j+XVn0IQXGdHgzp A5rU0k/G7Opn3zXBOATJfjGTpUr3xvw7zhB/rMRNQUljOfGoYhIjywddxU3/FYXQgW1R 0ivA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=fV7ccHviKdT5N80jdO6dd53UrhaOoJRUZfoKN6BxqsE=; b=bvjh1LoGqIKs1/O20mb5eHOjlfjKNkihZF3/xLdiMJT2HEgxbvKJR1XVSTV2/Ix4sl Z2EmEnEJkYI4itgdc+X1twF1xIwtPi2BQ1irFa905zFgNK7dtpO3HplsKCM3CANP/dOx IpVNV2YxtzUgcCfvy5tCJI7WTZlno4MiaHMRzknPNesVobFW2TcPFyfSvj2DfSeobAn8 4BM/k4kuCmiHSj1SGZSLS9sIQAu4Xxun2NA4ksJ8NH+UKCIBcxV+DpuUrswwn8wgf5l4 r/vlHQUghFoBj550aVnRVktBqObtT0uHvhrZU1S4FY7Tmv1FpMREEZpzGgLuqI7Y91YE dzcQ== X-Gm-Message-State: AOUpUlGYkan6pA48NCP47bS8gR5BJ70jmGAg3ce/Hqjfa2SJgrlvjXV7 EHZHjo8HVj+eJAwWPRwqhMM= X-Google-Smtp-Source: AA+uWPy6vcTzUAx6YLOZHLeQmfHiU/XnBKinO5EnzEw4Np9dSqyD6LeO4YZOvE16oFjNeYpeM1+foQ== X-Received: by 2002:adf:e841:: with SMTP id d1-v6mr4494752wrn.269.1534145660783; Mon, 13 Aug 2018 00:34:20 -0700 (PDT) Received: from ubuntu.home ([2a02:8071:6a3:700:542c:ff11:9c97:a518]) by smtp.gmail.com with ESMTPSA id b8-v6sm19382806wrw.22.2018.08.13.00.34.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 13 Aug 2018 00:34:19 -0700 (PDT) From: Simon Goldschmidt To: Marek Vasut Date: Mon, 13 Aug 2018 09:33:49 +0200 Message-Id: <20180813073351.29293-7-simon.k.r.goldschmidt@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20180813073351.29293-1-simon.k.r.goldschmidt@gmail.com> References: <20180813073351.29293-1-simon.k.r.goldschmidt@gmail.com> Cc: Tom Rini , u-boot@lists.denx.de Subject: [U-Boot] [PATCH v3 6/8] arm: socfpga: gen5: combine some init code for SPL and U-Boot X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Some of the code for low level system initialization in SPL's board_init_f() and U-Boot's arch_early_init_r() is the same, so let's combine it into a single function called from both. Signed-off-by: Simon Goldschmidt --- Changes in v3: this patch is new in v3 Changes in v2: None arch/arm/mach-socfpga/include/mach/misc.h | 4 +++ arch/arm/mach-socfpga/misc_gen5.c | 33 +++++++++++++---------- arch/arm/mach-socfpga/spl_gen5.c | 30 +-------------------- 3 files changed, 24 insertions(+), 43 deletions(-) diff --git a/arch/arm/mach-socfpga/include/mach/misc.h b/arch/arm/mach-socfpga/include/mach/misc.h index 7fe77ac8d8..aa7f38d4ea 100644 --- a/arch/arm/mach-socfpga/include/mach/misc.h +++ b/arch/arm/mach-socfpga/include/mach/misc.h @@ -27,6 +27,10 @@ unsigned int shared_uart_com_port(const void *blob); unsigned int uart_com_port(const void *blob); #endif +#ifdef CONFIG_TARGET_SOCFPGA_GEN5 +void socfpga_init_bus_mapping(void); +#endif + void do_bridge_reset(int enable); #endif /* _MISC_H_ */ diff --git a/arch/arm/mach-socfpga/misc_gen5.c b/arch/arm/mach-socfpga/misc_gen5.c index 848551c73f..32af1a9084 100644 --- a/arch/arm/mach-socfpga/misc_gen5.c +++ b/arch/arm/mach-socfpga/misc_gen5.c @@ -175,6 +175,24 @@ static void socfpga_nic301_slave_ns(void) writel(0x1, &nic301_regs->sdrdata); } +void socfpga_init_bus_mapping(void) +{ + socfpga_bridges_reset(1); + + socfpga_nic301_slave_ns(); + + /* + * Private components security: + * U-Boot : configure private timer, global timer and cpu component + * access as non secure for kernel stage (as required by Linux) + */ + setbits_le32(&scu_regs->sacr, 0xfff); + + /* Configure the L2 controller to make SDRAM start at 0 */ + writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ + writel(0x1, &pl310->pl310_addr_filter_start); +} + static u32 iswgrp_handoff[8]; int arch_early_init_r(void) @@ -193,20 +211,7 @@ int arch_early_init_r(void) for (i = 0; i < 8; i++) /* Cache initial SW setting regs */ iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); - socfpga_bridges_reset(1); - - socfpga_nic301_slave_ns(); - - /* - * Private components security: - * U-Boot : configure private timer, global timer and cpu component - * access as non secure for kernel stage (as required by Linux) - */ - setbits_le32(&scu_regs->sacr, 0xfff); - - /* Configure the L2 controller to make SDRAM start at 0 */ - writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ - writel(0x1, &pl310->pl310_addr_filter_start); + socfpga_init_bus_mapping(); /* Add device descriptor to FPGA device table */ socfpga_fpga_add(); diff --git a/arch/arm/mach-socfpga/spl_gen5.c b/arch/arm/mach-socfpga/spl_gen5.c index 0e685f6ee5..631905fbee 100644 --- a/arch/arm/mach-socfpga/spl_gen5.c +++ b/arch/arm/mach-socfpga/spl_gen5.c @@ -5,7 +5,6 @@ #include #include -#include #include #include #include @@ -17,8 +16,6 @@ #include #include #include -#include -#include #include #include #include @@ -26,12 +23,6 @@ DECLARE_GLOBAL_DATA_PTR; -static struct pl310_regs *const pl310 = - (struct pl310_regs *)CONFIG_SYS_PL310_BASE; -static struct scu_registers *scu_regs = - (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; -static struct nic301_registers *nic301_regs = - (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS; static const struct socfpga_system_manager *sysmgr_regs = (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; @@ -72,16 +63,6 @@ u32 spl_boot_mode(const u32 boot_device) } #endif -static void socfpga_nic301_slave_ns(void) -{ - writel(0x1, &nic301_regs->lwhps2fpgaregs); - writel(0x1, &nic301_regs->hps2fpgaregs); - writel(0x1, &nic301_regs->acp); - writel(0x1, &nic301_regs->rom); - writel(0x1, &nic301_regs->ocram); - writel(0x1, &nic301_regs->sdrdata); -} - void board_init_f(ulong dummy) { const struct cm_config *cm_default_cfg = cm_get_default_config(); @@ -103,14 +84,7 @@ void board_init_f(ulong dummy) memset(__bss_start, 0, __bss_end - __bss_start); - socfpga_nic301_slave_ns(); - - /* Configure ARM MPU SNSAC register. */ - setbits_le32(&scu_regs->sacr, 0xfff); - - /* Remap SDRAM to 0x0 */ - writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ - writel(0x1, &pl310->pl310_addr_filter_start); + socfpga_init_bus_mapping(); debug("Freezing all I/O banks\n"); /* freeze all IO banks */ @@ -118,8 +92,6 @@ void board_init_f(ulong dummy) /* Put everything into reset but L4WD0. */ socfpga_per_reset_all(); - /* Put FPGA bridges into reset too. */ - socfpga_bridges_reset(1); socfpga_per_reset(SOCFPGA_RESET(SDR), 0); socfpga_per_reset(SOCFPGA_RESET(UART0), 0);