From patchwork Tue May 8 22:18:40 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcel Ziswiler X-Patchwork-Id: 910510 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ziswiler.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40gYpN0h4Mz9s2t for ; Wed, 9 May 2018 08:20:28 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id D28EBC21EC5; Tue, 8 May 2018 22:19:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id DF399C21E52; Tue, 8 May 2018 22:19:02 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 09B0AC21C38; Tue, 8 May 2018 22:19:00 +0000 (UTC) Received: from mout.perfora.net (mout.perfora.net [74.208.4.197]) by lists.denx.de (Postfix) with ESMTPS id 323DDC21C38 for ; Tue, 8 May 2018 22:19:00 +0000 (UTC) Received: from localhost.net ([84.227.20.26]) by mrelay.perfora.net (mreueus001 [74.208.5.2]) with ESMTPA (Nemesis) id 0MI7Zo-1fIw653DGI-003rpi; Wed, 09 May 2018 00:18:56 +0200 From: Marcel Ziswiler To: u-boot@lists.denx.de Date: Wed, 9 May 2018 00:18:40 +0200 Message-Id: <20180508221840.32463-4-marcel@ziswiler.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180508221840.32463-1-marcel@ziswiler.com> References: <20180508221840.32463-1-marcel@ziswiler.com> X-Provags-ID: V03:K1:59ObspDA6vFXDa5qC9DkFlI3S5/K3aoMnklLlcMFOwIz0m0Pxpc WssN92d1tDCQMhfiJZai6ztBA0mNiIdSgvBHqU5ksewXsdcphokU/j8dMreKZOBQQqrKwrQ d+mWhZI/4v0BtQaztFChUwta/2VrOlFVfncIGQkPnTYV4EHkgAcQxSDukYOEY5Y1klcnQtx fqgnmjZqkybF1qKsshFCQ== X-UI-Out-Filterresults: notjunk:1; V01:K0:bVeE+6+KZws=:ABSx+wwQNlEseXwYrf2cG7 35iMyU6xXJbN8kR8AQziaIUFuURy8aRCJbdfaBFaAdcHcEKXOYng3ohxZv2HRI8W2q3Km0h5Z ekjqLByiR4Kh9gfUpuEFwyb9ceGfTq8Q/+DKNKbLYnLFd3msLSCK5UexfEUzZGvTwWRlBq2FV QNHMUYLnfloRWBFq6OgySp5W0r6NVhkzoqShzaz2u3vHfbaAkk8CR7UGVnZSXqW+EYPaRZ0vW 4kO3mx+/ITs3PZgA+W4edFJ/7X7sKYGnBUrcDubHpG0/AWSI4pe+Rek3ckHXUMLQkGsf6wULm yT59kBnhxPhVaGkVNI3qJ266YnPi3WW1RAziSTIjqBddEGrZeMmpv61cilhOIsRlG/U4vk0NA rHhP9i9TRc+LQBXSdMQEY/vTp1QdJIgKhX2YO+k54C1J8W8TosKbl6WS8rl3ZT/4cREbQa8gr Coh2JnnYoJttSzlDP34EP50MRfbsauFP+K8cCaL0uK2yvlPDXvkL+cHJ4SdxBJQYf59U+e1px rk4BdbZ782Ubg1dk7+7Wa/M9eqafY0hqAngiAK5SEAKSZk/PlvwZ6BE4e9kHlmbuO8fPkYX/O hyngtiZrQAJ0vsdtKzKkfm/OU42LCNu2t2SQSky9hya9R9OJ5LZUrk1qX+Kiq38Qg4VuVkWP5 3Tu/1jk+2xRoHGFNo5+WOXRofqkNR0+RjqdOBvodHAZKE2jkBrIx6Md0c5Te0fHxGdyk= Cc: Marcel Ziswiler Subject: [U-Boot] [PATCH v4 3/3] apalis_t30: fix optional pcie port reset for reliable pcie operation X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Marcel Ziswiler Allow optionally bringing up the Apalis type specific 4 lane PCIe port as well as the PCIe switch as found on the Apalis Evaluation board. In order to avoid violating the PCIe reset timing do this by overriding the tegra_pcie_board_port_reset() function. Note however that both the Apalis type specific 4 lane PCIe port as well as the regular Apalis PCIe port are also left disabled in the device tree by default. Signed-off-by: Marcel Ziswiler Acked-by: Stephen Warren --- Changes in v4: - Fix spelling of losing vs. loosing. Changes in v3: - Updated copyright period to 2014-2018. - Added a blank line after declarations as warned by patman. - Added Stephen's acked-by. - Rebased and resend as series so far never got applied! Changes in v2: - Stick to struct tegra_pcie_port as suggested by Stephen. - Introduce proper CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT Kconfig option as suggested by Stephen. - Improved the ifdef vs. if curly braces sequencing as suggested by Stephen. - Keep PCIe port reset status in order to safeguard for future changes to the port reset order or even allow for re-initialisation should that ever be implemented in the higher levels of the driver model. board/toradex/apalis_t30/Kconfig | 9 ++++++ board/toradex/apalis_t30/apalis_t30.c | 57 ++++++++++++++++++++++++++++++++++- 2 files changed, 65 insertions(+), 1 deletion(-) diff --git a/board/toradex/apalis_t30/Kconfig b/board/toradex/apalis_t30/Kconfig index 16224daa12..9cd497091d 100644 --- a/board/toradex/apalis_t30/Kconfig +++ b/board/toradex/apalis_t30/Kconfig @@ -25,6 +25,15 @@ config TDX_CFG_BLOCK_PART config TDX_CFG_BLOCK_OFFSET default "-512" +config APALIS_T30_PCIE_EVALBOARD_INIT + bool "Apalis Evaluation Board PCIe Initialisation" + help + Bring up the Apalis type specific 4 lane PCIe port as well as the + Apalis PCIe port with the PCIe switch as found on the Apalis + Evaluation board. Note that by default both those ports are also left + disabled in the device tree which needs changing as well for this to + actually work. + source "board/toradex/common/Kconfig" endif diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index 28830b6345..ace9c5b168 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * (C) Copyright 2014-2016 + * (C) Copyright 2014-2018 * Marcel Ziswiler */ @@ -13,6 +13,7 @@ #include #include #include +#include #include "../common/tdx-common.h" #include "pinmux-config-apalis_t30.h" @@ -22,6 +23,13 @@ DECLARE_GLOBAL_DATA_PTR; #define PMU_I2C_ADDRESS 0x2D #define MAX_I2C_RETRY 3 +#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT +#define PEX_PERST_N TEGRA_GPIO(S, 7) /* Apalis GPIO7 */ +#define RESET_MOCI_CTRL TEGRA_GPIO(I, 4) + +static int pci_reset_status; +#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */ + int arch_misc_init(void) { if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) == @@ -106,6 +114,53 @@ int tegra_pcie_board_init(void) return err; } +#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT + gpio_request(PEX_PERST_N, "PEX_PERST_N"); + gpio_request(RESET_MOCI_CTRL, "RESET_MOCI_CTRL"); +#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */ + return 0; } + +void tegra_pcie_board_port_reset(struct tegra_pcie_port *port) +{ + int index = tegra_pcie_port_index_of_port(port); + + if (index == 2) { /* I210 Gigabit Ethernet Controller (On-module) */ + tegra_pcie_port_reset(port); + } +#ifdef CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT + /* + * Apalis PCIe aka port 1 and Apalis Type Specific 4 Lane PCIe aka port + * 0 share the same RESET_MOCI therefore only assert it once for both + * ports to avoid losing the previously brought up port again. + */ + else if ((index == 1) || (index == 0)) { + /* only do it once per init cycle */ + if (pci_reset_status % 2 == 0) { + /* + * Reset PLX PEX 8605 PCIe Switch plus PCIe devices on + * Apalis Evaluation Board + */ + gpio_direction_output(PEX_PERST_N, 0); + gpio_direction_output(RESET_MOCI_CTRL, 0); + + /* + * Must be asserted for 100 ms after power and clocks + * are stable + */ + mdelay(100); + + gpio_set_value(PEX_PERST_N, 1); + /* + * Err_5: PEX_REFCLK_OUTpx/nx Clock Outputs is not + * Guaranteed Until 900 us After PEX_PERST# De-assertion + */ + mdelay(1); + gpio_set_value(RESET_MOCI_CTRL, 1); + } + pci_reset_status++; + } +#endif /* CONFIG_APALIS_T30_PCIE_EVALBOARD_INIT */ +} #endif /* CONFIG_PCI_TEGRA */