From patchwork Wed Mar 21 12:59:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugeniy Paltsev X-Patchwork-Id: 888819 X-Patchwork-Delegate: alexey.brodkin@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=synopsys.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 405qqH24W4z9s0w for ; Thu, 22 Mar 2018 00:08:11 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id E2E3EC21E4F; Wed, 21 Mar 2018 13:05:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 42390C21F02; Wed, 21 Mar 2018 13:01:42 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3BB96C21E4F; Wed, 21 Mar 2018 12:59:42 +0000 (UTC) Received: from smtprelay.synopsys.com (us01smtprelay-2.synopsys.com [198.182.47.9]) by lists.denx.de (Postfix) with ESMTPS id D451BC21EBB for ; Wed, 21 Mar 2018 12:59:38 +0000 (UTC) Received: from mailhost.synopsys.com (mailhost3.synopsys.com [10.12.238.238]) by smtprelay.synopsys.com (Postfix) with ESMTP id 8404424E12DE for ; Wed, 21 Mar 2018 05:59:37 -0700 (PDT) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 6AB5D33A2; Wed, 21 Mar 2018 05:59:37 -0700 (PDT) Received: from paltsev-e7480.internal.synopsys.com (unknown [10.121.8.67]) by mailhost.synopsys.com (Postfix) with ESMTP id 36CCD33A1; Wed, 21 Mar 2018 05:59:36 -0700 (PDT) From: Eugeniy Paltsev To: uboot-snps-arc@synopsys.com Date: Wed, 21 Mar 2018 15:59:03 +0300 Message-Id: <20180321125905.14897-19-Eugeniy.Paltsev@synopsys.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180321125905.14897-1-Eugeniy.Paltsev@synopsys.com> References: <20180321125905.14897-1-Eugeniy.Paltsev@synopsys.com> Cc: u-boot@lists.denx.de, Alexey Brodkin , Eugeniy Paltsev Subject: [U-Boot] [PATCH v2 18/20] ARC: cache: add additional configuration checks X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add additional cache configuration checks and note about supported configurations. Signed-off-by: Eugeniy Paltsev --- arch/arc/lib/cache.c | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 5d7583d868..fd70ce8efe 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -85,6 +85,66 @@ * enabling force function inline with '__attribute__((always_inline))' gcc * attribute to avoid any function call (and BLINK store) between cache flush * and disable. + * + * + * [ NOTE 2 ]: + * As of today we only support the following cache configurations on ARC. + * Other configurations may exist in HW (for example, since version 3.0 HS + * supports SL$ (L2 system level cache) disable) but we don't support it in SW. + * Configuration 1: + * ______________________ + * | | + * | ARC CPU | + * |______________________| + * ___|___ ___|___ + * | | | | + * | L1 I$ | | L1 D$ | + * |_______| |_______| + * on/off on/off + * ___|______________|____ + * | | + * | main memory | + * |______________________| + * + * Configuration 2: + * ______________________ + * | | + * | ARC CPU | + * |______________________| + * ___|___ ___|___ + * | | | | + * | L1 I$ | | L1 D$ | + * |_______| |_______| + * on/off on/off + * ___|______________|____ + * | | + * | L2 (SL$) | + * |______________________| + * always must be on + * ___|______________|____ + * | | + * | main memory | + * |______________________| + * + * Configuration 3: + * ______________________ + * | | + * | ARC CPU | + * |______________________| + * ___|___ ___|___ + * | | | | + * | L1 I$ | | L1 D$ | + * |_______| |_______| + * on/off must be on + * ___|______________|____ _______ + * | | | | + * | L2 (SL$) |-----| IOC | + * |______________________| |_______| + * always must be on on/off + * ___|______________|____ + * | | + * | main memory | + * |______________________| */ DECLARE_GLOBAL_DATA_PTR; @@ -308,6 +368,14 @@ static void arc_ioc_setup(void) /* IOC Aperture size is equal to DDR size */ long ap_size = CONFIG_SYS_SDRAM_SIZE; + /* Unsupported configuration. See [ NOTE 2 ] for more details. */ + if (!slc_exists()) + panic("Try to enable IOC but SLC is not present"); + + /* Unsupported configuration. See [ NOTE 2 ] for more details. */ + if (!dcache_enabled()) + panic("Try to enable IOC but L1 D$ is disabled"); + flush_n_invalidate_dcache_all(); if (!is_power_of_2(ap_size) || ap_size < 4096) @@ -338,6 +406,13 @@ static void read_decode_cache_bcr_arcv2(void) if (slc_exists()) { slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); gd->arch.slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; + + /* + * We don't support configuration where L1 I$ or L1 D$ is + * absent but SL$ exists. See [ NOTE 2 ] for more details. + */ + if (!icache_exists() || !dcache_exists()) + panic("Unsupported cache configuration: SLC exists but one of L1 caches is absent"); } #endif /* CONFIG_ISA_ARCV2 */