From patchwork Wed Mar 21 12:59:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugeniy Paltsev X-Patchwork-Id: 888836 X-Patchwork-Delegate: alexey.brodkin@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=synopsys.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 405qv710r7z9s02 for ; Thu, 22 Mar 2018 00:11:30 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 45678C21E8A; Wed, 21 Mar 2018 13:04:11 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C88B6C21E44; Wed, 21 Mar 2018 13:00:59 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C6B8BC21E44; Wed, 21 Mar 2018 12:59:39 +0000 (UTC) Received: from smtprelay.synopsys.com (us01smtprelay-2.synopsys.com [198.182.60.111]) by lists.denx.de (Postfix) with ESMTPS id C1B93C21E18 for ; Wed, 21 Mar 2018 12:59:35 +0000 (UTC) Received: from mailhost.synopsys.com (mailhost3.synopsys.com [10.12.238.238]) by smtprelay.synopsys.com (Postfix) with ESMTP id 719BA10C0394 for ; Wed, 21 Mar 2018 05:59:34 -0700 (PDT) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 604403394; Wed, 21 Mar 2018 05:59:34 -0700 (PDT) Received: from paltsev-e7480.internal.synopsys.com (unknown [10.121.8.67]) by mailhost.synopsys.com (Postfix) with ESMTP id 3142C3392; Wed, 21 Mar 2018 05:59:33 -0700 (PDT) From: Eugeniy Paltsev To: uboot-snps-arc@synopsys.com Date: Wed, 21 Mar 2018 15:59:01 +0300 Message-Id: <20180321125905.14897-17-Eugeniy.Paltsev@synopsys.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180321125905.14897-1-Eugeniy.Paltsev@synopsys.com> References: <20180321125905.14897-1-Eugeniy.Paltsev@synopsys.com> Cc: u-boot@lists.denx.de, Alexey Brodkin , Eugeniy Paltsev Subject: [U-Boot] [PATCH v2 16/20] ARC: cache: fix SLC operations when SLC is bypassed for data X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" If L1 data cache is disabled SL$ is bypassed for data and all load/store requests are sent directly to main memory. If L1 instructiona cache is disabled SL$ is NOT bypassed for instructions and all instruction requests are fetched through SLC. Signed-off-by: Eugeniy Paltsev --- arch/arc/lib/cache.c | 39 ++++++++++++++++++++++++++++----------- 1 file changed, 28 insertions(+), 11 deletions(-) diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 7052895bb7..a5aae3d232 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -168,6 +168,15 @@ static inline bool slc_exists(void) return false; } +static inline bool slc_data_bypass(void) +{ + /* + * If L1 data cache is disabled SL$ is bypassed and all load/store + * requests are sent directly to main memory. + */ + return !dcache_enabled(); +} + static inline bool ioc_exists(void) { if (is_isa_arcv2()) { @@ -412,7 +421,13 @@ void invalidate_icache_all(void) { __ic_entire_invalidate(); - if (is_isa_arcv2()) + /* + * If SL$ is bypassed for data it is used only for instructions, + * so we need to invalidate it too. + * TODO: HS 3.0 supports SLC disable so we need to check slc + * enable/disable status here. + */ + if (is_isa_arcv2() && slc_data_bypass()) __slc_entire_op(OP_INV); } @@ -520,14 +535,15 @@ void invalidate_dcache_range(unsigned long start, unsigned long end) return; /* - * ARCv1 -> call __dc_line_op - * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op - * ARCv2 && IOC enabled -> nothing + * ARCv1 -> call __dc_line_op + * ARCv2 && L1 D$ disabled -> nothing + * ARCv2 && L1 D$ enabled && IOC enabled -> nothing + * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op */ if (!is_isa_arcv2() || !ioc_enabled()) __dc_line_op(start, end - start, OP_INV); - if (is_isa_arcv2() && !ioc_enabled()) + if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass()) __slc_rgn_op(start, end - start, OP_INV); } @@ -537,14 +553,15 @@ void flush_dcache_range(unsigned long start, unsigned long end) return; /* - * ARCv1 -> call __dc_line_op - * ARCv2 && no IOC -> call __dc_line_op; call __slc_rgn_op - * ARCv2 && IOC enabled -> nothing + * ARCv1 -> call __dc_line_op + * ARCv2 && L1 D$ disabled -> nothing + * ARCv2 && L1 D$ enabled && IOC enabled -> nothing + * ARCv2 && L1 D$ enabled && no IOC -> call __dc_line_op; call __slc_rgn_op */ if (!is_isa_arcv2() || !ioc_enabled()) __dc_line_op(start, end - start, OP_FLUSH); - if (is_isa_arcv2() && !ioc_enabled()) + if (is_isa_arcv2() && !ioc_enabled() && !slc_data_bypass()) __slc_rgn_op(start, end - start, OP_FLUSH); } @@ -563,7 +580,7 @@ void flush_n_invalidate_dcache_all(void) { __dc_entire_op(OP_FLUSH_N_INV); - if (is_isa_arcv2()) + if (is_isa_arcv2() && !slc_data_bypass()) __slc_entire_op(OP_FLUSH_N_INV); } @@ -571,6 +588,6 @@ void flush_dcache_all(void) { __dc_entire_op(OP_FLUSH); - if (is_isa_arcv2()) + if (is_isa_arcv2() && !slc_data_bypass()) __slc_entire_op(OP_FLUSH); }