From patchwork Wed Mar 21 12:58:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eugeniy Paltsev X-Patchwork-Id: 888797 X-Patchwork-Delegate: alexey.brodkin@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=synopsys.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 405qj40gtlz9s0w for ; Thu, 22 Mar 2018 00:02:47 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 18D7AC21DF8; Wed, 21 Mar 2018 13:01:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7BCDCC21E02; Wed, 21 Mar 2018 12:59:50 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 98D05C21EA6; Wed, 21 Mar 2018 12:59:31 +0000 (UTC) Received: from smtprelay.synopsys.com (smtprelay.synopsys.com [198.182.47.9]) by lists.denx.de (Postfix) with ESMTPS id 0E18DC21E08 for ; Wed, 21 Mar 2018 12:59:28 +0000 (UTC) Received: from mailhost.synopsys.com (mailhost3.synopsys.com [10.12.238.238]) by smtprelay.synopsys.com (Postfix) with ESMTP id B9A6224E1370 for ; Wed, 21 Mar 2018 05:59:26 -0700 (PDT) Received: from mailhost.synopsys.com (localhost [127.0.0.1]) by mailhost.synopsys.com (Postfix) with ESMTP id 9FBAF335C; Wed, 21 Mar 2018 05:59:26 -0700 (PDT) Received: from paltsev-e7480.internal.synopsys.com (unknown [10.121.8.67]) by mailhost.synopsys.com (Postfix) with ESMTP id 74641335B; Wed, 21 Mar 2018 05:59:25 -0700 (PDT) From: Eugeniy Paltsev To: uboot-snps-arc@synopsys.com Date: Wed, 21 Mar 2018 15:58:56 +0300 Message-Id: <20180321125905.14897-12-Eugeniy.Paltsev@synopsys.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180321125905.14897-1-Eugeniy.Paltsev@synopsys.com> References: <20180321125905.14897-1-Eugeniy.Paltsev@synopsys.com> Cc: u-boot@lists.denx.de, Alexey Brodkin , Eugeniy Paltsev Subject: [U-Boot] [PATCH v2 11/20] ARC: cache: get rid of [slc, pae, icache, dcache]_exists global variables X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" There is the problem with current implementation if we start u-boot from ROM, as we use cache global variables before ther initialization, so these variables are overwritten when we copy .data section from ROM. So use icache_exists(), dcache_exists(), slc_exists(), pae_exists() functions which check BCRs every time instead of corresponding global variables. Signed-off-by: Eugeniy Paltsev --- arch/arc/lib/cache.c | 67 +++++++++++++++++++++++++++++++++------------------- 1 file changed, 43 insertions(+), 24 deletions(-) diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index f147674ae8..1b74f55ab7 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -94,7 +94,6 @@ #define DC_CTRL_CACHE_DISABLE BIT(0) #define DC_CTRL_INV_MODE_FLUSH BIT(6) #define DC_CTRL_FLUSH_STATUS BIT(8) -#define CACHE_VER_NUM_MASK 0xF #define OP_INV BIT(0) #define OP_FLUSH BIT(1) @@ -112,20 +111,16 @@ * relocation but will be used after being zeroed. */ int l1_line_sz __section(".data"); -bool dcache_exists __section(".data") = false; -bool icache_exists __section(".data") = false; #define CACHE_LINE_MASK (~(l1_line_sz - 1)) int slc_line_sz __section(".data"); -bool slc_exists __section(".data") = false; bool ioc_exists __section(".data") = false; -bool pae_exists __section(".data") = false; /* To force enable IOC set ioc_enable to 'true' */ bool ioc_enable __section(".data") = false; -void read_decode_mmu_bcr(void) +static inline bool pae_exists(void) { /* TODO: should we compare mmu version from BCR and from CONFIG? */ #if (CONFIG_ARC_MMU_VER >= 4) @@ -133,15 +128,46 @@ void read_decode_mmu_bcr(void) mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR); - pae_exists = !!mmu4.fields.pae; + if (mmu4.fields.pae) + return true; #endif /* (CONFIG_ARC_MMU_VER >= 4) */ + + return false; +} + +static inline bool icache_exists(void) +{ + union bcr_di_cache ibcr; + + ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); + return !!ibcr.fields.ver; +} + +static inline bool dcache_exists(void) +{ + union bcr_di_cache dbcr; + + dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); + return !!dbcr.fields.ver; +} + +static inline bool slc_exists(void) +{ + if (is_isa_arcv2()) { + union bcr_generic sbcr; + + sbcr.word = read_aux_reg(ARC_BCR_SLC); + return !!sbcr.fields.ver; + } + + return false; } static void __slc_entire_op(const int op) { unsigned int ctrl; - if (!slc_exists) + if (!slc_exists()) return; ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); @@ -182,7 +208,7 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) unsigned int ctrl; unsigned long end; - if (!slc_exists) + if (!slc_exists()) return; /* @@ -263,12 +289,9 @@ static void read_decode_cache_bcr_arcv2(void) union bcr_slc_cfg slc_cfg; union bcr_clust_cfg cbcr; - union bcr_generic sbcr; - sbcr.word = read_aux_reg(ARC_BCR_SLC); - if (sbcr.fields.ver) { + if (slc_exists()) { slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); - slc_exists = true; slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64; } @@ -286,7 +309,6 @@ void read_decode_cache_bcr(void) ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); if (ibcr.fields.ver) { - icache_exists = true; l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len; if (!ic_line_sz) panic("Instruction exists but line length is 0\n"); @@ -294,7 +316,6 @@ void read_decode_cache_bcr(void) dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); if (dbcr.fields.ver) { - dcache_exists = true; l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len; if (!dc_line_sz) panic("Data cache exists but line length is 0\n"); @@ -314,20 +335,18 @@ void cache_init(void) if (is_isa_arcv2() && ioc_exists) arc_ioc_setup(); - read_decode_mmu_bcr(); - /* * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist * only if PAE exists in current HW. So we had to check pae_exist * before using them. */ - if (is_isa_arcv2() && slc_exists && pae_exists) + if (is_isa_arcv2() && slc_exists() && pae_exists()) slc_upper_region_init(); } int icache_status(void) { - if (!icache_exists) + if (!icache_exists()) return 0; if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) @@ -338,14 +357,14 @@ int icache_status(void) void icache_enable(void) { - if (icache_exists) + if (icache_exists()) write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & ~IC_CTRL_CACHE_DISABLE); } void icache_disable(void) { - if (icache_exists) + if (icache_exists()) write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | IC_CTRL_CACHE_DISABLE); } @@ -378,7 +397,7 @@ void invalidate_icache_all(void) int dcache_status(void) { - if (!dcache_exists) + if (!dcache_exists()) return 0; if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) @@ -389,7 +408,7 @@ int dcache_status(void) void dcache_enable(void) { - if (!dcache_exists) + if (!dcache_exists()) return; write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & @@ -398,7 +417,7 @@ void dcache_enable(void) void dcache_disable(void) { - if (!dcache_exists) + if (!dcache_exists()) return; write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |