From patchwork Mon Jan 29 06:36:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 867023 X-Patchwork-Delegate: marek.vasut@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zVKYQ1k8hz9s75 for ; Mon, 29 Jan 2018 17:36:56 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 6235EC21E63; Mon, 29 Jan 2018 06:36:45 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 66347C21E18; Mon, 29 Jan 2018 06:36:42 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A901BC21E18; Mon, 29 Jan 2018 06:36:41 +0000 (UTC) Received: from mailout.pepperl-fuchs.com (mailout.pepperl-fuchs.com [212.21.166.229]) by lists.denx.de (Postfix) with ESMTPS id 9859DC21C4F for ; Mon, 29 Jan 2018 06:36:40 +0000 (UTC) Received: from PFDE-CAS2.EU.P-F.BIZ (pfde-cas2.eu.p-f.biz [172.24.5.134]) by mailout.pepperl-fuchs.com (Postfix) with ESMTP id 4963B81D48; Mon, 29 Jan 2018 07:36:40 +0100 (CET) Received: from localhost.localdomain (172.24.114.233) by PFDE-CAS2.EU.P-F.BIZ (172.24.5.134) with Microsoft SMTP Server (TLS) id 14.3.301.0; Mon, 29 Jan 2018 07:36:39 +0100 From: Simon Goldschmidt To: Marek Vasut Date: Mon, 29 Jan 2018 07:36:37 +0100 Message-ID: <20180129063637.18347-1-sgoldschmidt@de.pepperl-fuchs.com> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 X-Originating-IP: [172.24.114.233] X-EXCLAIMER-MD-CONFIG: 1e262833-c6b8-4d86-a546-40bddc43f2e2 Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH 1/1] arm: socfpga: fix qspi flash compatible (add "spi-flash") X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch adds "spi-flash" to the compatible list of the qspi flash chip for all socfpga boards. This is required to make qspi work on these boards on top of the recent fixes. Without the "spi-flash" compatible string for the flash chip, the speed cannot be read and a speed of 0Hz is used (which results in a divide-by-zero on these boards). Signed-off-by: Simon Goldschmidt --- arch/arm/dts/socfpga_arria5_socdk.dts | 2 +- arch/arm/dts/socfpga_cyclone5_is1.dts | 2 +- arch/arm/dts/socfpga_cyclone5_socdk.dts | 2 +- arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts index 1e91a65af6..4e4b619f4f 100644 --- a/arch/arm/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/dts/socfpga_arria5_socdk.dts @@ -88,7 +88,7 @@ u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "n25q00", "spi-flash"; reg = <0>; /* chip select */ spi-max-frequency = <50000000>; m25p,fast-read; diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts index 2e2b71fefb..ea323a16ca 100644 --- a/arch/arm/dts/socfpga_cyclone5_is1.dts +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts @@ -87,7 +87,7 @@ u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "n25q00", "spi-flash"; reg = <0>; /* chip select */ spi-max-frequency = <100000000>; m25p,fast-read; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 95a8e653d7..3af51134bb 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -98,7 +98,7 @@ u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "n25q00", "spi-flash"; reg = <0>; /* chip select */ spi-max-frequency = <100000000>; m25p,fast-read; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index e3ae8a8207..e612eeed4f 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -68,7 +68,7 @@ flash0: n25q00@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "n25q00", "spi-flash"; reg = <0>; /* chip select */ spi-max-frequency = <50000000>; m25p,fast-read;