| Message ID | 20180129063637.18347-1-sgoldschmidt@de.pepperl-fuchs.com |
|---|---|
| State | Accepted |
| Commit | a6fbf9455090bdfa4d92e8215e81bdf7bb397757 |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | [U-Boot,1/1] arm: socfpga: fix qspi flash compatible (add "spi-flash") | expand |
On 01/29/2018 07:36 AM, Simon Goldschmidt wrote: > This patch adds "spi-flash" to the compatible list of the qspi flash > chip for all socfpga boards. This is required to make qspi work on > these boards on top of the recent fixes. Without the "spi-flash" > compatible string for the flash chip, the speed cannot be read and a > speed of 0Hz is used (which results in a divide-by-zero on these > boards). > > Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> What's the status of the recent fixes ? Are they in already ? Applied anyway, thanks. > --- > arch/arm/dts/socfpga_arria5_socdk.dts | 2 +- > arch/arm/dts/socfpga_cyclone5_is1.dts | 2 +- > arch/arm/dts/socfpga_cyclone5_socdk.dts | 2 +- > arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 +- > 4 files changed, 4 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts > index 1e91a65af6..4e4b619f4f 100644 > --- a/arch/arm/dts/socfpga_arria5_socdk.dts > +++ b/arch/arm/dts/socfpga_arria5_socdk.dts > @@ -88,7 +88,7 @@ > u-boot,dm-pre-reloc; > #address-cells = <1>; > #size-cells = <1>; > - compatible = "n25q00"; > + compatible = "n25q00", "spi-flash"; > reg = <0>; /* chip select */ > spi-max-frequency = <50000000>; > m25p,fast-read; > diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts > index 2e2b71fefb..ea323a16ca 100644 > --- a/arch/arm/dts/socfpga_cyclone5_is1.dts > +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts > @@ -87,7 +87,7 @@ > u-boot,dm-pre-reloc; > #address-cells = <1>; > #size-cells = <1>; > - compatible = "n25q00"; > + compatible = "n25q00", "spi-flash"; > reg = <0>; /* chip select */ > spi-max-frequency = <100000000>; > m25p,fast-read; > diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts > index 95a8e653d7..3af51134bb 100644 > --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts > +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts > @@ -98,7 +98,7 @@ > u-boot,dm-pre-reloc; > #address-cells = <1>; > #size-cells = <1>; > - compatible = "n25q00"; > + compatible = "n25q00", "spi-flash"; > reg = <0>; /* chip select */ > spi-max-frequency = <100000000>; > m25p,fast-read; > diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts > index e3ae8a8207..e612eeed4f 100644 > --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts > +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts > @@ -68,7 +68,7 @@ > flash0: n25q00@0 { > #address-cells = <1>; > #size-cells = <1>; > - compatible = "n25q00"; > + compatible = "n25q00", "spi-flash"; > reg = <0>; /* chip select */ > spi-max-frequency = <50000000>; > m25p,fast-read; >
On 29.01.2018 11:35, Marek Vasut wrote: > On 01/29/2018 07:36 AM, Simon Goldschmidt wrote: >> This patch adds "spi-flash" to the compatible list of the qspi flash >> chip for all socfpga boards. This is required to make qspi work on >> these boards on top of the recent fixes. Without the "spi-flash" >> compatible string for the flash chip, the speed cannot be read and a >> speed of 0Hz is used (which results in a divide-by-zero on these >> boards). >> >> Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> > What's the status of the recent fixes ? Are they in already ? Yes, they were applied via u-boot-spi. Everything should work now. > > Applied anyway, thanks. > >> --- >> arch/arm/dts/socfpga_arria5_socdk.dts | 2 +- >> arch/arm/dts/socfpga_cyclone5_is1.dts | 2 +- >> arch/arm/dts/socfpga_cyclone5_socdk.dts | 2 +- >> arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 +- >> 4 files changed, 4 insertions(+), 4 deletions(-) >> >> diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts >> index 1e91a65af6..4e4b619f4f 100644 >> --- a/arch/arm/dts/socfpga_arria5_socdk.dts >> +++ b/arch/arm/dts/socfpga_arria5_socdk.dts >> @@ -88,7 +88,7 @@ >> u-boot,dm-pre-reloc; >> #address-cells = <1>; >> #size-cells = <1>; >> - compatible = "n25q00"; >> + compatible = "n25q00", "spi-flash"; >> reg = <0>; /* chip select */ >> spi-max-frequency = <50000000>; >> m25p,fast-read; >> diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts >> index 2e2b71fefb..ea323a16ca 100644 >> --- a/arch/arm/dts/socfpga_cyclone5_is1.dts >> +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts >> @@ -87,7 +87,7 @@ >> u-boot,dm-pre-reloc; >> #address-cells = <1>; >> #size-cells = <1>; >> - compatible = "n25q00"; >> + compatible = "n25q00", "spi-flash"; >> reg = <0>; /* chip select */ >> spi-max-frequency = <100000000>; >> m25p,fast-read; >> diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts >> index 95a8e653d7..3af51134bb 100644 >> --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts >> +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts >> @@ -98,7 +98,7 @@ >> u-boot,dm-pre-reloc; >> #address-cells = <1>; >> #size-cells = <1>; >> - compatible = "n25q00"; >> + compatible = "n25q00", "spi-flash"; >> reg = <0>; /* chip select */ >> spi-max-frequency = <100000000>; >> m25p,fast-read; >> diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts >> index e3ae8a8207..e612eeed4f 100644 >> --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts >> +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts >> @@ -68,7 +68,7 @@ >> flash0: n25q00@0 { >> #address-cells = <1>; >> #size-cells = <1>; >> - compatible = "n25q00"; >> + compatible = "n25q00", "spi-flash"; >> reg = <0>; /* chip select */ >> spi-max-frequency = <50000000>; >> m25p,fast-read; >> >
On 01/29/2018 12:56 PM, Simon Goldschmidt wrote: > On 29.01.2018 11:35, Marek Vasut wrote: >> On 01/29/2018 07:36 AM, Simon Goldschmidt wrote: >>> This patch adds "spi-flash" to the compatible list of the qspi flash >>> chip for all socfpga boards. This is required to make qspi work on >>> these boards on top of the recent fixes. Without the "spi-flash" >>> compatible string for the flash chip, the speed cannot be read and a >>> speed of 0Hz is used (which results in a divide-by-zero on these >>> boards). >>> >>> Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> >> What's the status of the recent fixes ? Are they in already ? > > Yes, they were applied via u-boot-spi. Everything should work now. Can you test u-boot/master once they land, so we're sure ? Thanks
Pepperl+Fuchs GmbH, Mannheim Geschaeftsfuehrer/Managing Directors: Dr.-Ing. Gunther Kegel (Vors./CEO), Werner Guthier, Mehmet Hatiboglu Vorsitzender des Aufsichtsrats/Chairman of the supervisory board: Claus Michael Registergericht/Register Court: AG Mannheim HRB 4713 On 29.01.2018 13:01, Marek Vasut wrote: > On 01/29/2018 12:56 PM, Simon Goldschmidt wrote: >> On 29.01.2018 11:35, Marek Vasut wrote: >>> On 01/29/2018 07:36 AM, Simon Goldschmidt wrote: >>>> This patch adds "spi-flash" to the compatible list of the qspi flash >>>> chip for all socfpga boards. This is required to make qspi work on >>>> these boards on top of the recent fixes. Without the "spi-flash" >>>> compatible string for the flash chip, the speed cannot be read and a >>>> speed of 0Hz is used (which results in a divide-by-zero on these >>>> boards). >>>> >>>> Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> >>> What's the status of the recent fixes ? Are they in already ? >> Yes, they were applied via u-boot-spi. Everything should work now. > Can you test u-boot/master once they land, so we're sure ? Thanks Yes, I'll upgrade the version we use internally to v2018.03 RCs as soon as they are tagged. Wichtiger Hinweis: Diese E-Mail einschliesslich ihrer Anhaenge enthaelt vertrauliche und rechtlich geschuetzte Informationen, die nur fuer den Adressaten bestimmt sind. Sollten Sie nicht der bezeichnete Adressat sein, so teilen Sie dies bitte dem Absender umgehend mit und loeschen Sie diese Nachricht und ihre Anhaenge. Die unbefugte Weitergabe, das Anfertigen von Kopien und jede Veraenderung der E-Mail ist untersagt. Der Absender haftet nicht fuer Inhalte von veraenderten E-Mails. Important Information: This e-mail message including its attachments contains confidential and legally protected information solely intended for the addressee. If you are not the intended addressee of this message, please contact the addresser immediately and delete this message including its attachments. The unauthorized dissemination, copying and change of this e-mail are strictly forbidden. The addresser shall not be liable for the content of such changed e-mails.
diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts b/arch/arm/dts/socfpga_arria5_socdk.dts index 1e91a65af6..4e4b619f4f 100644 --- a/arch/arm/dts/socfpga_arria5_socdk.dts +++ b/arch/arm/dts/socfpga_arria5_socdk.dts @@ -88,7 +88,7 @@ u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "n25q00", "spi-flash"; reg = <0>; /* chip select */ spi-max-frequency = <50000000>; m25p,fast-read; diff --git a/arch/arm/dts/socfpga_cyclone5_is1.dts b/arch/arm/dts/socfpga_cyclone5_is1.dts index 2e2b71fefb..ea323a16ca 100644 --- a/arch/arm/dts/socfpga_cyclone5_is1.dts +++ b/arch/arm/dts/socfpga_cyclone5_is1.dts @@ -87,7 +87,7 @@ u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "n25q00", "spi-flash"; reg = <0>; /* chip select */ spi-max-frequency = <100000000>; m25p,fast-read; diff --git a/arch/arm/dts/socfpga_cyclone5_socdk.dts b/arch/arm/dts/socfpga_cyclone5_socdk.dts index 95a8e653d7..3af51134bb 100644 --- a/arch/arm/dts/socfpga_cyclone5_socdk.dts +++ b/arch/arm/dts/socfpga_cyclone5_socdk.dts @@ -98,7 +98,7 @@ u-boot,dm-pre-reloc; #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "n25q00", "spi-flash"; reg = <0>; /* chip select */ spi-max-frequency = <100000000>; m25p,fast-read; diff --git a/arch/arm/dts/socfpga_cyclone5_socrates.dts b/arch/arm/dts/socfpga_cyclone5_socrates.dts index e3ae8a8207..e612eeed4f 100644 --- a/arch/arm/dts/socfpga_cyclone5_socrates.dts +++ b/arch/arm/dts/socfpga_cyclone5_socrates.dts @@ -68,7 +68,7 @@ flash0: n25q00@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "n25q00"; + compatible = "n25q00", "spi-flash"; reg = <0>; /* chip select */ spi-max-frequency = <50000000>; m25p,fast-read;
This patch adds "spi-flash" to the compatible list of the qspi flash chip for all socfpga boards. This is required to make qspi work on these boards on top of the recent fixes. Without the "spi-flash" compatible string for the flash chip, the speed cannot be read and a speed of 0Hz is used (which results in a divide-by-zero on these boards). Signed-off-by: Simon Goldschmidt <sgoldschmidt@de.pepperl-fuchs.com> --- arch/arm/dts/socfpga_arria5_socdk.dts | 2 +- arch/arm/dts/socfpga_cyclone5_is1.dts | 2 +- arch/arm/dts/socfpga_cyclone5_socdk.dts | 2 +- arch/arm/dts/socfpga_cyclone5_socrates.dts | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-)