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[2003:5f:2c23:2401:62a4:4cff:fe5e:9229]) by smtp.gmail.com with ESMTPSA id p13sm7042758wmd.1.2016.09.25.11.05.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 25 Sep 2016 11:05:52 -0700 (PDT) From: Daniel Schwierzeck To: u-boot@lists.denx.de Date: Sun, 25 Sep 2016 20:05:24 +0200 Message-Id: <20160925180532.19800-2-daniel.schwierzeck@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20160925180532.19800-1-daniel.schwierzeck@gmail.com> References: <20160925180532.19800-1-daniel.schwierzeck@gmail.com> Cc: Marek Vasut , Purna Chandra Mandal , Wills Wang Subject: [U-Boot] [PATCH 1/9] MIPS: make inclusion of ROM exception vectors configurable X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds a compile time option to include code for static exception vectors. Static exception vectors are only needed, when the U-Boot entry point is equal to the CPU reset exception vector address. For instance this is the case when U-Boot is used as ROM in Qemu or booted from parallel NOR flash. When U-Boot is booted from RAM (e.g. loaded there by SPL), the exception vectors need to be setup dynamically, which is done in follow-up commits. Signed-off-by: Daniel Schwierzeck --- arch/mips/Kconfig | 21 +++++++++++++++++++++ arch/mips/cpu/start.S | 11 ++++++++--- arch/mips/mach-ath79/Kconfig | 2 ++ arch/mips/mach-pic32/Kconfig | 1 + 4 files changed, 32 insertions(+), 3 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 097ad58..709ac5c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -20,6 +20,7 @@ config TARGET_QEMU_MIPS select SUPPORTS_CPU_MIPS32_R2 select SUPPORTS_CPU_MIPS64_R1 select SUPPORTS_CPU_MIPS64_R2 + select ROM_EXCEPTION_VECTORS config TARGET_MALTA bool "Support malta" @@ -40,6 +41,7 @@ config TARGET_MALTA select SUPPORTS_CPU_MIPS64_R6 select SWAP_IO_SPACE select MIPS_L1_CACHE_SHIFT_6 + select ROM_EXCEPTION_VECTORS config TARGET_VCT bool "Support vct" @@ -47,6 +49,7 @@ config TARGET_VCT select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SYS_MIPS_CACHE_INIT_RAM_LOAD + select ROM_EXCEPTION_VECTORS config TARGET_DBAU1X00 bool "Support dbau1x00" @@ -55,6 +58,7 @@ config TARGET_DBAU1X00 select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SYS_MIPS_CACHE_INIT_RAM_LOAD + select ROM_EXCEPTION_VECTORS select MIPS_TUNE_4KC config TARGET_PB1X00 @@ -63,6 +67,7 @@ config TARGET_PB1X00 select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select SYS_MIPS_CACHE_INIT_RAM_LOAD + select ROM_EXCEPTION_VECTORS select MIPS_TUNE_4KC config ARCH_ATH79 @@ -91,6 +96,7 @@ config TARGET_BOSTON select SUPPORTS_CPU_MIPS64_R1 select SUPPORTS_CPU_MIPS64_R2 select SUPPORTS_CPU_MIPS64_R6 + select ROM_EXCEPTION_VECTORS config TARGET_XILFPGA bool "Support Imagination Xilfpga" @@ -103,6 +109,7 @@ config TARGET_XILFPGA select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 select MIPS_L1_CACHE_SHIFT_4 + select ROM_EXCEPTION_VECTORS help This supports IMGTEC MIPSfpga platform @@ -192,6 +199,20 @@ config CPU_MIPS64_R6 endchoice +menu "General setup" + +config ROM_EXCEPTION_VECTORS + bool "Build U-Boot image with exception vectors" + help + Enable this to include exception vectors in the U-Boot image. This is + required if the U-Boot entry point is equal to the address of the + CPU reset exception vector (e.g. U-Boot as ROM loader in Qemu, + U-Boot booted from parallel NOR flash). + Disable this, if the U-Boot image is booted from DRAM (e.g. by SPL). + In that case the image size will be reduced by 0x500 bytes. + +endmenu + menu "OS boot interface" config MIPS_BOOT_CMDLINE_LEGACY diff --git a/arch/mips/cpu/start.S b/arch/mips/cpu/start.S index 3f0fc12..108d2df 100644 --- a/arch/mips/cpu/start.S +++ b/arch/mips/cpu/start.S @@ -57,7 +57,6 @@ ENTRY(_start) b reset nop - .org 0x10 #if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG) /* * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to @@ -66,16 +65,20 @@ ENTRY(_start) * initial configuration for that EBU in order to access the flash * device with correct parameters. This config option is board-specific. */ + .org 0x10 .word CONFIG_SYS_XWAY_EBU_BOOTCFG .word 0x0 -#elif defined(CONFIG_MALTA) +#endif +#if defined(CONFIG_MALTA) /* * Linux expects the Board ID here. */ + .org 0x10 .word 0x00000420 # 0x420 (Malta Board with CoreLV) .word 0x00000000 #endif +#if defined(CONFIG_ROM_EXCEPTION_VECTORS) .org 0x200 /* TLB refill, 32 bit task */ 1: b 1b @@ -106,7 +109,9 @@ ENTRY(_start) 1: b 1b nop - .align 4 + .org 0x500 +#endif + reset: #if __mips_isa_rev >= 6 mfc0 t0, CP0_CONFIG, 5 diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig index 7d483aa..d982b0f 100644 --- a/arch/mips/mach-ath79/Kconfig +++ b/arch/mips/mach-ath79/Kconfig @@ -9,6 +9,7 @@ config SOC_AR933X select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 + select ROM_EXCEPTION_VECTORS select MIPS_TUNE_24KC help This supports QCA/Atheros ar933x family SOCs. @@ -27,6 +28,7 @@ config SOC_QCA953X select SUPPORTS_BIG_ENDIAN select SUPPORTS_CPU_MIPS32_R1 select SUPPORTS_CPU_MIPS32_R2 + select ROM_EXCEPTION_VECTORS select MIPS_TUNE_24KC help This supports QCA/Atheros qca953x family SOCs. diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig index 2e38bb7..8fad4cf 100644 --- a/arch/mips/mach-pic32/Kconfig +++ b/arch/mips/mach-pic32/Kconfig @@ -14,6 +14,7 @@ config SOC_PIC32MZDA select SUPPORTS_CPU_MIPS32_R2 select MIPS_L1_CACHE_SHIFT_4 select SYS_MIPS_CACHE_INIT_RAM_LOAD + select ROM_EXCEPTION_VECTORS help This supports Microchip PIC32MZ[DA] family of microcontrollers.