diff --git a/board/edb93xx/pll_cfg.h b/board/edb93xx/pll_cfg.h
index 0b6f469..39d6f5a 100644
--- a/board/edb93xx/pll_cfg.h
+++ b/board/edb93xx/pll_cfg.h
@@ -25,8 +25,7 @@
 #include <config.h>
 #include <asm/arch/ep93xx.h>
 
-#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) ||	\
-	defined(CONFIG_EDB9302A)
+#if defined(CONFIG_EDB9301)
 /*
  * fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2
  * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000,
@@ -39,7 +38,8 @@
 			3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT |	\
 			SYSCON_CLKSET1_NBYP1 |			\
 			1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT)
-#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||	\
+#elif defined(CONFIG_EDB9302) || defined(CONFIG_EDB9302A)	\
+	defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) ||	\
 	defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) ||	\
 	defined(CONFIG_EDB9315A)
 /*
diff --git a/board/edb93xx/sdram_cfg.h b/board/edb93xx/sdram_cfg.h
index 757b63c..5a5cf82 100644
--- a/board/edb93xx/sdram_cfg.h
+++ b/board/edb93xx/sdram_cfg.h
@@ -43,12 +43,13 @@
  * CLK cycle time min:
  *	@ CAS latency = 3: 7.5ns
  *	@ CAS latency = 2: 10ns
- * We're running at 66MHz (15ns cycle time) external bus speed (HCLK),
- * so it's safe to use CAS latency = 2
+ * We're running at 66MHz (EDB9301) / 100Mhz (EDB9302(a)) external
+ * bus speed (HCLK), with a cycle time of 15ns / 10ns, so it's safe
+ * to use CAS latency = 2
  *
  * RAS-to-CAS delay min:
  *	20ns
- * At 15ns cycle time, we use RAS-to-CAS delay = 2
+ * At 15ns/10ns cycle time, we use RAS-to-CAS delay = 2
  *
  * SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear
  * as four blocks of 8MB size, instead of eight blocks of 4MB size: