From patchwork Wed Feb 10 21:37:21 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 71723 X-Patchwork-Delegate: albert.aribaud@free.fr Return-Path: X-Original-To: wd@gemini.denx.de Delivered-To: wd@gemini.denx.de Received: from diddl.denx.de (diddl.denx.de [10.0.0.6]) by gemini.denx.de (Postfix) with ESMTP id DF514E917A2 for ; Wed, 10 Feb 2010 22:39:25 +0100 (CET) Received: from diddl.denx.de (localhost.localdomain [127.0.0.1]) by diddl.denx.de (Postfix) with ESMTP id D2853C7FA5C0 for ; Wed, 10 Feb 2010 22:39:25 +0100 (CET) Received: from pop.mnet-online.de by diddl.denx.de with POP3 (fetchmail-6.3.9) for (single-drop); Wed, 10 Feb 2010 22:39:25 +0100 (CET) Received: from murder (svr19.m-online.net [192.168.3.147]) by backend2 (Cyrus v2.2.12) with LMTPA; Wed, 10 Feb 2010 22:37:53 +0100 X-Sieve: CMU Sieve 2.2 Received: from mail.m-online.net (localhost [127.0.0.1]) by frontend3.pop.m-online.net (Cyrus v2.2.13) with LMTPA; Wed, 10 Feb 2010 22:37:53 +0100 Received: from scanner-3.m-online.net (scanner-3.m-online.net [192.168.1.20]) by mail.m-online.net (Postfix) with ESMTP id 3502220019C; Wed, 10 Feb 2010 22:37:53 +0100 (CET) Received: from mxin-3.m-online.net ([192.168.6.165]) by scanner-3.m-online.net (scanner-3.m-online.net [192.168.1.20]) (amavisd-new, port 10026) with ESMTP id 29381-01-3; Wed, 10 Feb 2010 22:37:52 +0100 (CET) Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by mxin-3.m-online.net (Postfix) with ESMTP id 0BE4746C0A1; Wed, 10 Feb 2010 22:37:50 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1B2DE2808A; Wed, 10 Feb 2010 22:37:47 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QHq9DDpLPQ3V; Wed, 10 Feb 2010 22:37:46 +0100 (CET) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id E3E042807C; Wed, 10 Feb 2010 22:37:42 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1EC3B28077 for ; Wed, 10 Feb 2010 22:37:40 +0100 (CET) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 1XMwIxELxBrQ for ; Wed, 10 Feb 2010 22:37:38 +0100 (CET) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from relay1-d.mail.gandi.net (relay1-d.mail.gandi.net [217.70.183.193]) by theia.denx.de (Postfix) with ESMTP id 0548828071 for ; Wed, 10 Feb 2010 22:37:36 +0100 (CET) Received: from d4rwin.no-ip.org (79.Red-88-19-186.staticIP.rima-tde.net [88.19.186.79]) by relay1-d.mail.gandi.net (Postfix) with ESMTPSA id 866BA255300; Wed, 10 Feb 2010 22:37:35 +0100 (CET) Received: by d4rwin.no-ip.org (Postfix, from userid 1000) id 1172F4CD52; Wed, 10 Feb 2010 22:37:21 +0100 (CET) Date: Wed, 10 Feb 2010 22:37:21 +0100 From: Matthias Kaehlcke To: Tom Message-ID: <20100210213721.GH374@darwin> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-06-14) Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH] edb9302(a): Tweak PLL settings X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.9 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de X-Virus-Scanned: by amavisd-new at m-online.net Previous code ran the edb9302(a) boards with the PLL same settings as the edb9301, at 166MHz core and 66MHz system bus clock. In difference to the edb9301 board the edb9302(a) is equipped with an EP9302 processor, which can be clocked at higher rates than the EP9301. Therefore we can configure the edb9302(a) with the same PLL settings as the other non-edb9301 boards, namely at 200MHz for the core and 100MHz for the system bus clock. Signed-off-by: Matthias Kaehlcke --- board/edb93xx/pll_cfg.h | 6 +++--- board/edb93xx/sdram_cfg.h | 7 ++++--- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/board/edb93xx/pll_cfg.h b/board/edb93xx/pll_cfg.h index 0b6f469..39d6f5a 100644 --- a/board/edb93xx/pll_cfg.h +++ b/board/edb93xx/pll_cfg.h @@ -25,8 +25,7 @@ #include #include -#if defined(CONFIG_EDB9301) || defined(CONFIG_EDB9302) || \ - defined(CONFIG_EDB9302A) +#if defined(CONFIG_EDB9301) /* * fclk_div: 2, nbyp1: 1, hclk_div: 5, pclk_div: 2 * pll1_x1: 294912000.000000, pll1_x2ip: 36864000.000000, @@ -39,7 +38,8 @@ 3 << SYSCON_CLKSET1_HCLK_DIV_SHIFT | \ SYSCON_CLKSET1_NBYP1 | \ 1 << SYSCON_CLKSET1_FCLK_DIV_SHIFT) -#elif defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) || \ +#elif defined(CONFIG_EDB9302) || defined(CONFIG_EDB9302A) \ + defined(CONFIG_EDB9307) || defined(CONFIG_EDB9307A) || \ defined CONFIG_EDB9312 || defined(CONFIG_EDB9315) || \ defined(CONFIG_EDB9315A) /* diff --git a/board/edb93xx/sdram_cfg.h b/board/edb93xx/sdram_cfg.h index 757b63c..5a5cf82 100644 --- a/board/edb93xx/sdram_cfg.h +++ b/board/edb93xx/sdram_cfg.h @@ -43,12 +43,13 @@ * CLK cycle time min: * @ CAS latency = 3: 7.5ns * @ CAS latency = 2: 10ns - * We're running at 66MHz (15ns cycle time) external bus speed (HCLK), - * so it's safe to use CAS latency = 2 + * We're running at 66MHz (EDB9301) / 100Mhz (EDB9302(a)) external + * bus speed (HCLK), with a cycle time of 15ns / 10ns, so it's safe + * to use CAS latency = 2 * * RAS-to-CAS delay min: * 20ns - * At 15ns cycle time, we use RAS-to-CAS delay = 2 + * At 15ns/10ns cycle time, we use RAS-to-CAS delay = 2 * * SROMLL = 1: Swap BA[1:0] with A[13:12], making the SDRAM appear * as four blocks of 8MB size, instead of eight blocks of 4MB size: