From patchwork Mon May 16 02:42:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2VpamllIEdhbyAo6auY5oOf5p2wKQ==?= X-Patchwork-Id: 1631253 X-Patchwork-Delegate: daniel.schwierzeck@googlemail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by bilbo.ozlabs.org (Postfix) with ESMTPS id 4L1k8b46dRz9s5V for ; Mon, 16 May 2022 12:43:43 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id E40ED84251; Mon, 16 May 2022 04:43:17 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=fail (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id 0999F8425C; Mon, 16 May 2022 04:43:01 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,RDNS_NONE, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.2 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id DC650841EC for ; Mon, 16 May 2022 04:42:48 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=weijie.gao@mediatek.com X-UUID: 96b9f52f5bac44749c2053a436bf30e1-20220516 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5, REQID:0f6f3b3e-d1a7-4c9e-acc4-28d5b2ec000b, OB:0, LO B:0,IP:0,URL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:-5 X-CID-META: VersionHash:2a19b09, CLOUDID:ab876aa7-eab7-4b74-a74d-5359964535a9, C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil ,QS:0,BEC:nil X-UUID: 96b9f52f5bac44749c2053a436bf30e1-20220516 Received: from mtkmbs10n2.mediatek.inc [(172.21.101.183)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1384491772; Mon, 16 May 2022 10:42:43 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Mon, 16 May 2022 10:42:41 +0800 Received: from mcddlt001.gcn.mediatek.inc (10.19.240.15) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Mon, 16 May 2022 10:42:41 +0800 From: Weijie Gao To: CC: GSS_MTK_Uboot_upstream , Daniel Schwierzeck , Stefan Roese , Weijie Gao Subject: [PATCH v5 06/25] mips: mtmips: add two reference boards for mt7621 Date: Mon, 16 May 2022 10:42:37 +0800 Message-ID: <1a9d1878f99a8e2a0a0677e63b5e068661f8c732.1652667687.git.weijie.gao@mediatek.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: References: MIME-Version: 1.0 X-MTK: N X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean The mt7621_rfb board supports integrated giga PHYs plus one external giga PHYs. It also has up to 512MiB DDR3, 16MB SPI-NOR, 3 mini PCI-e x1 slots, SDXC and USB. The mt7621_nand_rfb board is almost the same as mt7621_rfb board, but it uses NAND flash and SDXC is not available. Reviewed-by: Stefan Roese Reviewed-by: Daniel Schwierzeck Signed-off-by: Weijie Gao Reviewed-by: Daniel Schwierzeck --- v5 changes: Fix defconfig file names in MAINTAINERS Remove unused configs in defconfig files Move pinctrl default states to board dts files v4 changes: Modify defconfig files for booting from flash v3 changes: none v2 changes: Add config file for mt7621-rfb boards --- arch/mips/dts/Makefile | 2 + arch/mips/dts/mediatek,mt7621-nand-rfb.dts | 67 +++++++++++++++++ arch/mips/dts/mediatek,mt7621-rfb.dts | 82 +++++++++++++++++++++ arch/mips/mach-mtmips/mt7621/Kconfig | 20 ++++++ board/mediatek/mt7621/MAINTAINERS | 8 +++ board/mediatek/mt7621/Makefile | 3 + board/mediatek/mt7621/board.c | 6 ++ configs/mt7621_nand_rfb_defconfig | 83 ++++++++++++++++++++++ configs/mt7621_rfb_defconfig | 82 +++++++++++++++++++++ 9 files changed, 353 insertions(+) create mode 100644 arch/mips/dts/mediatek,mt7621-nand-rfb.dts create mode 100644 arch/mips/dts/mediatek,mt7621-rfb.dts create mode 100644 board/mediatek/mt7621/MAINTAINERS create mode 100644 board/mediatek/mt7621/Makefile create mode 100644 board/mediatek/mt7621/board.c create mode 100644 configs/mt7621_nand_rfb_defconfig create mode 100644 configs/mt7621_rfb_defconfig diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 95144b24dc..1b179116c9 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -16,6 +16,8 @@ dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb dtb-$(CONFIG_BOARD_MT7620_RFB) += mediatek,mt7620-rfb.dtb dtb-$(CONFIG_BOARD_MT7620_MT7530_RFB) += mediatek,mt7620-mt7530-rfb.dtb +dtb-$(CONFIG_BOARD_MT7621_RFB) += mediatek,mt7621-rfb.dtb +dtb-$(CONFIG_BOARD_MT7621_NAND_RFB) += mediatek,mt7621-nand-rfb.dtb dtb-$(CONFIG_BOARD_MT7628_RFB) += mediatek,mt7628-rfb.dtb dtb-$(CONFIG_BOARD_GARDENA_SMART_GATEWAY_MT7688) += gardena-smart-gateway-mt7688.dtb dtb-$(CONFIG_BOARD_LINKIT_SMART_7688) += linkit-smart-7688.dtb diff --git a/arch/mips/dts/mediatek,mt7621-nand-rfb.dts b/arch/mips/dts/mediatek,mt7621-nand-rfb.dts new file mode 100644 index 0000000000..67ba298b0a --- /dev/null +++ b/arch/mips/dts/mediatek,mt7621-nand-rfb.dts @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 MediaTek Inc. All rights reserved. + * + * Author: Weijie Gao + */ + +/dts-v1/; + +#include "mt7621.dtsi" + +/ { + compatible = "mediatek,mt7621-nand-rfb", "mediatek,mt7621-soc"; + model = "MediaTek MT7621 RFB (NAND)"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = &uart0; + }; +}; + +&pinctrl { + state_default: pin_state { + nand { + groups = "spi", "sdxc"; + function = "nand"; + }; + + gpios { + groups = "i2c", "uart3", "pcie reset"; + function = "gpio"; + }; + + wdt { + groups = "wdt"; + function = "wdt rst"; + }; + + jtag { + groups = "jtag"; + function = "jtag"; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +ð { + status = "okay"; +}; + +&ssusb { + status = "okay"; +}; + +&u3phy { + status = "okay"; +}; diff --git a/arch/mips/dts/mediatek,mt7621-rfb.dts b/arch/mips/dts/mediatek,mt7621-rfb.dts new file mode 100644 index 0000000000..ff7eaf0f20 --- /dev/null +++ b/arch/mips/dts/mediatek,mt7621-rfb.dts @@ -0,0 +1,82 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 MediaTek Inc. All rights reserved. + * + * Author: Weijie Gao + */ + +/dts-v1/; + +#include "mt7621.dtsi" + +/ { + compatible = "mediatek,mt7621-rfb", "mediatek,mt7621-soc"; + model = "MediaTek MT7621 RFB (SPI-NOR)"; + + aliases { + serial0 = &uart0; + spi0 = &spi; + }; + + chosen { + stdout-path = &uart0; + }; +}; + +&pinctrl { + state_default: pin_state { + gpios { + groups = "i2c", "uart3", "pcie reset"; + function = "gpio"; + }; + + wdt { + groups = "wdt"; + function = "wdt rst"; + }; + + jtag { + groups = "jtag"; + function = "jtag"; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&gpio { + status = "okay"; +}; + +&spi { + status = "okay"; + num-cs = <2>; + + spi-flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "jedec,spi-nor"; + spi-max-frequency = <25000000>; + reg = <0>; + }; +}; + +ð { + status = "okay"; +}; + +&mmc { + cap-sd-highspeed; + + status = "okay"; +}; + +&ssusb { + status = "okay"; +}; + +&u3phy { + status = "okay"; +}; diff --git a/arch/mips/mach-mtmips/mt7621/Kconfig b/arch/mips/mach-mtmips/mt7621/Kconfig index 37d512c68f..008a28f991 100644 --- a/arch/mips/mach-mtmips/mt7621/Kconfig +++ b/arch/mips/mach-mtmips/mt7621/Kconfig @@ -79,6 +79,26 @@ config MT7621_BOOT_FROM_NAND choice prompt "Board select" +config BOARD_MT7621_RFB + bool "MediaTek MT7621 RFB (SPI-NOR)" + help + The reference design of MT7621A (WS3010) booting from SPI-NOR flash. + The board can be configured with DDR2 (64MiB~256MiB) or DDR3 + (128MiB~512MiB). The board has 16 MiB SPI-NOR flash, built-in MT7530 + GbE switch, 1 UART, 1 USB 2.0 host, 1 USB 3.0 host, 1 SDXC, 3 PCIe + sockets, 1 RGMII to external GbE PHY, 2 audio jacks (in/out), + JTAG pins and expansion GPIO pins. + +config BOARD_MT7621_NAND_RFB + bool "MediaTek MT7621 RFB (NAND)" + help + The reference design of MT7621A (WS3010) booting from NAND flash. + The board can be configured with DDR2 (64MiB~256MiB) or DDR3 + (128MiB~512MiB). The board has 128 MiB parallel NAND flash, built-in + MT7530 GbE switch, 1 UART, 1 USB 2.0 host, 1 USB 3.0 host, 3 PCIe + sockets, 1 RGMII to external GbE PHY, 2 audio jacks (in/out), + JTAG pins and expansion GPIO pins. + endchoice config SYS_CONFIG_NAME diff --git a/board/mediatek/mt7621/MAINTAINERS b/board/mediatek/mt7621/MAINTAINERS new file mode 100644 index 0000000000..f83141cea1 --- /dev/null +++ b/board/mediatek/mt7621/MAINTAINERS @@ -0,0 +1,8 @@ +MT7621_RFB BOARD +M: Weijie Gao +S: Maintained +F: board/mediatek/mt7621 +F: configs/mt7621_rfb_defconfig +F: configs/mt7621_nand_rfb_defconfig +F: arch/mips/dts/mediatek,mt7621-rfb.dts +F: arch/mips/dts/mediatek,mt7621-nand-rfb.dts diff --git a/board/mediatek/mt7621/Makefile b/board/mediatek/mt7621/Makefile new file mode 100644 index 0000000000..db129c5aba --- /dev/null +++ b/board/mediatek/mt7621/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += board.o diff --git a/board/mediatek/mt7621/board.c b/board/mediatek/mt7621/board.c new file mode 100644 index 0000000000..0496f3f806 --- /dev/null +++ b/board/mediatek/mt7621/board.c @@ -0,0 +1,6 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2022 MediaTek Inc. All rights reserved. + * + * Author: Weijie Gao + */ diff --git a/configs/mt7621_nand_rfb_defconfig b/configs/mt7621_nand_rfb_defconfig new file mode 100644 index 0000000000..f733427eb1 --- /dev/null +++ b/configs/mt7621_nand_rfb_defconfig @@ -0,0 +1,83 @@ +CONFIG_MIPS=y +CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x1000 +CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7621-nand-rfb" +CONFIG_SPL_SERIAL=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x100000 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xbe000c00 +CONFIG_DEBUG_UART_CLOCK=50000000 +CONFIG_SYS_LOAD_ADDR=0x83000000 +CONFIG_ARCH_MTMIPS=y +CONFIG_SOC_MT7621=y +CONFIG_MT7621_BOOT_FROM_NAND=y +CONFIG_BOARD_MT7621_NAND_RFB=y +# CONFIG_MIPS_CACHE_SETUP is not set +# CONFIG_MIPS_CACHE_DISABLE is not set +CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_NAND_BASE=y +CONFIG_SPL_NAND_IDENT=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_DM is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_PART=y +# CONFIG_CMD_PINMUX is not set +CONFIG_CMD_USB=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +# CONFIG_I2C is not set +# CONFIG_INPUT is not set +CONFIG_MMC=y +# CONFIG_MMC_QUIRKS is not set +# CONFIG_MMC_HW_PARTITIONING is not set +CONFIG_MMC_MTK=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_MTD_RAW_NAND=y +CONFIG_NAND_MT7621=y +CONFIG_SYS_NAND_ONFI_DETECTION=y +CONFIG_MEDIATEK_ETH=y +CONFIG_PHY=y +CONFIG_PHY_MTK_TPHY=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_SYSRESET_RESETCTL=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_STORAGE=y +CONFIG_WDT=y +CONFIG_WDT_MT7621=y +CONFIG_FAT_WRITE=y +# CONFIG_BINMAN_FDT is not set +CONFIG_LZMA=y +# CONFIG_GZIP is not set +CONFIG_SPL_LZMA=y diff --git a/configs/mt7621_rfb_defconfig b/configs/mt7621_rfb_defconfig new file mode 100644 index 0000000000..ae62360e63 --- /dev/null +++ b/configs/mt7621_rfb_defconfig @@ -0,0 +1,82 @@ +CONFIG_MIPS=y +CONFIG_SYS_MALLOC_LEN=0x100000 +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x1000 +CONFIG_DEFAULT_DEVICE_TREE="mediatek,mt7621-rfb" +CONFIG_SPL_SERIAL=y +CONFIG_SPL_SYS_MALLOC_F_LEN=0x40000 +CONFIG_SPL=y +CONFIG_DEBUG_UART_BASE=0xbe000c00 +CONFIG_DEBUG_UART_CLOCK=50000000 +CONFIG_SYS_LOAD_ADDR=0x83000000 +CONFIG_ARCH_MTMIPS=y +CONFIG_SOC_MT7621=y +# CONFIG_MIPS_CACHE_SETUP is not set +# CONFIG_MIPS_CACHE_DISABLE is not set +CONFIG_RESTORE_EXCEPTION_VECTOR_BASE=y +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEBUG_UART=y +CONFIG_TPL_SYS_MALLOC_F_LEN=0x1000 +CONFIG_FIT=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_NOR_SUPPORT=y +CONFIG_TPL=y +# CONFIG_TPL_FRAMEWORK is not set +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_CRC32 is not set +# CONFIG_CMD_DM is not set +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MMC=y +CONFIG_CMD_PART=y +# CONFIG_CMD_PINMUX is not set +CONFIG_CMD_SPI=y +# CONFIG_CMD_NFS is not set +CONFIG_DOS_PARTITION=y +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_ISO_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_NET_RANDOM_ETHADDR=y +# CONFIG_I2C is not set +# CONFIG_INPUT is not set +CONFIG_MMC=y +# CONFIG_MMC_QUIRKS is not set +# CONFIG_MMC_HW_PARTITIONING is not set +CONFIG_MMC_MTK=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_BAR=y +CONFIG_SPI_FLASH_EON=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_ISSI=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_SPI_FLASH_XMC=y +CONFIG_SPI_FLASH_XTX=y +CONFIG_MEDIATEK_ETH=y +CONFIG_PHY=y +CONFIG_PHY_MTK_TPHY=y +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SPI=y +CONFIG_MT7621_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_RESETCTL=y +CONFIG_WDT=y +CONFIG_WDT_MT7621=y +# CONFIG_BINMAN_FDT is not set +CONFIG_LZMA=y +# CONFIG_GZIP is not set +CONFIG_SPL_LZMA=y