From patchwork Mon Apr 12 06:59:18 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vincent Chen X-Patchwork-Id: 1465134 X-Patchwork-Delegate: uboot@andestech.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256 header.s=google header.b=Ugn/5rCw; dkim-atps=neutral Received: from phobos.denx.de (phobos.denx.de [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4FJlxx26JMz9sWP for ; Mon, 12 Apr 2021 20:55:17 +1000 (AEST) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 5123D81FAB; Mon, 12 Apr 2021 12:54:36 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="Ugn/5rCw"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id AEB1B808C5; Mon, 12 Apr 2021 08:59:35 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de X-Spam-Level: X-Spam-Status: No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,SPF_HELO_NONE autolearn=unavailable autolearn_force=no version=3.4.2 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 4B61480050 for ; Mon, 12 Apr 2021 08:59:31 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=vincent.chen@sifive.com Received: by mail-pf1-x433.google.com with SMTP id s11so8601603pfm.1 for ; Sun, 11 Apr 2021 23:59:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id; bh=VAXswGlbgyCN6B5uGUto0k6BY5dkUIvCC+fc4PUJZH8=; b=Ugn/5rCw4cAvb8TNwKGXx288RyuuIV3QkQWa62KY9J/RAVeELNoJ0yQX9sTaze/VWh k9QdoADJFykJhDGp45U4n78n9Mpe0MxUmUm39gJd0FGa9WkC1H8LG/RQdyXL8FFGyqTp k64jqbVjEl+upQqREnIgobHfJlGj0lTPL8IuL7bH757of+/td+u/9qUjvbYPF/HR+bbb MSZkEARBtmhzMvxuI1eHJ5Pb2+kqDvY4w9nfRgT4f/jgGn3xpDsUmD4YP00asUWGUC52 qU8hEDysXH+eXmtjxJY2i2FTmACU6lGNXF+q0zk074lJTqno+WLlACuSNVc4hPAuPB3z qAHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=VAXswGlbgyCN6B5uGUto0k6BY5dkUIvCC+fc4PUJZH8=; b=T7rtJo57nLG1Z0I2izRGbuy26MJ+G4AJZRr9Wey/2o1vLsujZHuU+eY2AMdmhffy+E EDw1DbYtYx5QlLmqotHOoVmdVUE6s+oz4Jz0ZR6wxCuxu6trIcB2/2l2F0jmHDC54Cyr oS7zz9VTDBTY+FgB9Z4KvrNKIY/D5D2y8QF+8r+Nt0G9PHVnSGzFciXuEi6wOfNU1elM Jwu0N7sAK3eZ/jmNhQNCq5k7CAn4HHpfgUdd+AMo+N1L9WRrqNTcrv6Qkpfd+YE6igD1 a6NPzwABw29c+7OTDu64QLpnZCkGPqFkdHuM8Z1vEB4Q57r3tRd2ufp1je2JS6N6nrtv CRXQ== X-Gm-Message-State: AOAM531jkX9hZOkRAw2I+VFx2KUay/KNQs/N4kL5bz2N/FROiFeWOPpA hV69vpZl9t+fhJvX8gezGpfJRw== X-Google-Smtp-Source: ABdhPJy9NkqNGrhO3QvRJELxJm6KzjfZPZmZ8bO0aT4wDyF8YPpjWcZuaSCnGjfaNn/Yrl5I8j34bw== X-Received: by 2002:a63:a47:: with SMTP id z7mr22680656pgk.350.1618210769700; Sun, 11 Apr 2021 23:59:29 -0700 (PDT) Received: from VincentChen-ThinkPad-T480s.internal.sifive.com (114-34-229-221.HINET-IP.hinet.net. [114.34.229.221]) by smtp.gmail.com with ESMTPSA id g10sm1585651pfj.137.2021.04.11.23.59.27 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 11 Apr 2021 23:59:29 -0700 (PDT) From: Vincent Chen To: sjg@chromium.org, hs@denx.de Cc: u-boot@lists.denx.de, Vincent Chen Subject: [PATCH] pwm: sifive: make set_config() and set_enable() work properly Date: Mon, 12 Apr 2021 14:59:18 +0800 Message-Id: <1618210758-10291-1-git-send-email-vincent.chen@sifive.com> X-Mailer: git-send-email 2.7.4 X-Mailman-Approved-At: Mon, 12 Apr 2021 12:54:24 +0200 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.4 at phobos.denx.de X-Virus-Status: Clean The pwm_sifive_set_config() and pwm_sifive_set_enable() cannot work properly due to the wrong implementations. It will cause the u-boot PWM command to not work as expected. The bugs will be resolved in this patch. Signed-off-by: Vincent Chen --- drivers/pwm/pwm-sifive.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/drivers/pwm/pwm-sifive.c b/drivers/pwm/pwm-sifive.c index 01212d6..b9813a3 100644 --- a/drivers/pwm/pwm-sifive.c +++ b/drivers/pwm/pwm-sifive.c @@ -38,6 +38,9 @@ #define PWM_SIFIVE_SIZE_PWMCMP 4 #define PWM_SIFIVE_CMPWIDTH 16 +#define PWM_SIFIVE_CHANNEL_ENABLE_VAL 0 +#define PWM_SIFIVE_CHANNEL_DISABLE_VAL 0xffff + DECLARE_GLOBAL_DATA_PTR; struct pwm_sifive_regs { @@ -77,7 +80,7 @@ static int pwm_sifive_set_config(struct udevice *dev, uint channel, */ scale_pow = lldiv((uint64_t)priv->freq * period_ns, 1000000000); scale = clamp(ilog2(scale_pow) - PWM_SIFIVE_CMPWIDTH, 0, 0xf); - val |= FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale); + val |= (FIELD_PREP(PWM_SIFIVE_PWMCFG_SCALE, scale) | PWM_SIFIVE_PWMCFG_EN_ALWAYS); /* * The problem of output producing mixed setting as mentioned at top, @@ -88,6 +91,7 @@ static int pwm_sifive_set_config(struct udevice *dev, uint channel, num = (u64)duty_ns * (1U << PWM_SIFIVE_CMPWIDTH); frac = DIV_ROUND_CLOSEST_ULL(num, period_ns); frac = min(frac, (1U << PWM_SIFIVE_CMPWIDTH) - 1); + frac = (1U << PWM_SIFIVE_CMPWIDTH) - 1 - frac; writel(val, priv->base + regs->cfg); writel(frac, priv->base + regs->cmp0 + channel * @@ -100,18 +104,15 @@ static int pwm_sifive_set_enable(struct udevice *dev, uint channel, bool enable) { struct pwm_sifive_priv *priv = dev_get_priv(dev); const struct pwm_sifive_regs *regs = &priv->data->regs; - u32 val; debug("%s: Enable '%s'\n", __func__, dev->name); - if (enable) { - val = readl(priv->base + regs->cfg); - val |= PWM_SIFIVE_PWMCFG_EN_ALWAYS; - writel(val, priv->base + regs->cfg); - } else { - writel(0, priv->base + regs->cmp0 + channel * - PWM_SIFIVE_SIZE_PWMCMP); - } + if (enable) + writel(PWM_SIFIVE_CHANNEL_ENABLE_VAL, priv->base + + regs->cmp0 + channel * PWM_SIFIVE_SIZE_PWMCMP); + else + writel(PWM_SIFIVE_CHANNEL_DISABLE_VAL, priv->base + + regs->cmp0 + channel * PWM_SIFIVE_SIZE_PWMCMP); return 0; }