diff mbox series

[6/7] board: sifive: add HiFive Unmatched board support

Message ID 1615470589-130546-7-git-send-email-green.wan@sifive.com
State Superseded
Delegated to: Andes
Headers show
Series Add FU740 chip and HiFive Unmatched board support | expand

Commit Message

Green Wan March 11, 2021, 1:49 p.m. UTC 
Add dts, defconfig and board support for HiFive Unmatched.

Signed-off-by: Green Wan <green.wan@sifive.com>
---
 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489 ++++++++++++++++++++
 arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi    |   40 +
 arch/riscv/dts/hifive-unmatched-a00.dts            |  263 ++++
 board/sifive/fu540/Kconfig                         |    1 -
 board/sifive/fu540/fu540.c                         |    2 +-
 board/sifive/hifive_unmatched_fu740/Kconfig        |   50 +
 board/sifive/hifive_unmatched_fu740/MAINTAINERS    |    9 +
 board/sifive/hifive_unmatched_fu740/Makefile       |    9 +
 .../hifive-unmatched-fu740.c                       |   24 +
 board/sifive/hifive_unmatched_fu740/spl.c          |   85 ++
 configs/sifive_hifive_unmatched_fu740_defconfig    |   57 +
 doc/board/sifive/fu540.rst                         |   19 +-
 doc/board/sifive/hifive_unmatched_fu740.rst        |  532 +++++++
 drivers/reset/Kconfig                              |    2 +-
 include/configs/sifive-fu540.h                     |    5 -
 include/configs/sifive-hifive-unmatched-fu740.h    |   88 ++
 16 files changed, 2656 insertions(+), 19 deletions(-)
 create mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
 create mode 100644 arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
 create mode 100644 arch/riscv/dts/hifive-unmatched-a00.dts
 create mode 100644 board/sifive/hifive_unmatched_fu740/Kconfig
 create mode 100644 board/sifive/hifive_unmatched_fu740/MAINTAINERS
 create mode 100644 board/sifive/hifive_unmatched_fu740/Makefile
 create mode 100644 board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c
 create mode 100644 board/sifive/hifive_unmatched_fu740/spl.c
 create mode 100644 configs/sifive_hifive_unmatched_fu740_defconfig
 create mode 100644 doc/board/sifive/hifive_unmatched_fu740.rst
 create mode 100644 include/configs/sifive-hifive-unmatched-fu740.h

Comments

Bin Meng March 11, 2021, 2:20 p.m. UTC | #1 
On Thu, Mar 11, 2021 at 9:50 PM Green Wan <green.wan@sifive.com> wrote:
>
> Add dts, defconfig and board support for HiFive Unmatched.
>
> Signed-off-by: Green Wan <green.wan@sifive.com>
> ---
>  arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489 ++++++++++++++++++++
>  arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi    |   40 +
>  arch/riscv/dts/hifive-unmatched-a00.dts            |  263 ++++
>  board/sifive/fu540/Kconfig                         |    1 -
>  board/sifive/fu540/fu540.c                         |    2 +-

It looks these fu540 changes are not needed?

>  board/sifive/hifive_unmatched_fu740/Kconfig        |   50 +
>  board/sifive/hifive_unmatched_fu740/MAINTAINERS    |    9 +
>  board/sifive/hifive_unmatched_fu740/Makefile       |    9 +
>  .../hifive-unmatched-fu740.c                       |   24 +
>  board/sifive/hifive_unmatched_fu740/spl.c          |   85 ++
>  configs/sifive_hifive_unmatched_fu740_defconfig    |   57 +
>  doc/board/sifive/fu540.rst                         |   19 +-

here?

>  doc/board/sifive/hifive_unmatched_fu740.rst        |  532 +++++++
>  drivers/reset/Kconfig                              |    2 +-
>  include/configs/sifive-fu540.h                     |    5 -

and here?

>  include/configs/sifive-hifive-unmatched-fu740.h    |   88 ++
>  16 files changed, 2656 insertions(+), 19 deletions(-)
>  create mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
>  create mode 100644 arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
>  create mode 100644 arch/riscv/dts/hifive-unmatched-a00.dts
>  create mode 100644 board/sifive/hifive_unmatched_fu740/Kconfig
>  create mode 100644 board/sifive/hifive_unmatched_fu740/MAINTAINERS
>  create mode 100644 board/sifive/hifive_unmatched_fu740/Makefile
>  create mode 100644 board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c
>  create mode 100644 board/sifive/hifive_unmatched_fu740/spl.c
>  create mode 100644 configs/sifive_hifive_unmatched_fu740_defconfig
>  create mode 100644 doc/board/sifive/hifive_unmatched_fu740.rst
>  create mode 100644 include/configs/sifive-hifive-unmatched-fu740.h
>
> diff --git a/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
> new file mode 100644
> index 0000000..4209491
> --- /dev/null
> +++ b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi

[snip]

> diff --git a/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
> new file mode 100644
> index 0000000..3dcd2b4
> --- /dev/null
> +++ b/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
> @@ -0,0 +1,40 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2020-2021 SiFive, Inc
> + */
> +
> +#include "fu740-c000-u-boot.dtsi"
> +#include "fu740-hifive-unmatched-a00-ddr.dtsi"
> +
> +/ {
> +       aliases {
> +               spi0 = &spi0;
> +       };
> +
> +       memory@80000000 {
> +               u-boot,dm-spl;
> +       };
> +
> +       hfclk {
> +               u-boot,dm-spl;
> +       };
> +
> +       rtcclk {
> +               u-boot,dm-spl;
> +       };
> +
> +};
> +
> +&clint {
> +       clocks = <&rtcclk>;
> +};
> +
> +&spi0 {
> +       mmc@0 {
> +               u-boot,dm-spl;
> +       };
> +};
> +
> +&gpio {
> +       u-boot,dm-spl;
> +};
> diff --git a/arch/riscv/dts/hifive-unmatched-a00.dts b/arch/riscv/dts/hifive-unmatched-a00.dts
> new file mode 100644
> index 0000000..92410b4
> --- /dev/null
> +++ b/arch/riscv/dts/hifive-unmatched-a00.dts
> @@ -0,0 +1,263 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/* Copyright (c) 2019-2021 SiFive, Inc */
> +
> +#include "fu740-c000.dtsi"
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
> +#define RTCCLK_FREQ            1000000
> +
> +/ {
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +       model = "SiFive HiFive Unmatched A00";
> +       compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
> +                    "sifive,fu740";
> +
> +       chosen {
> +               stdout-path = "serial0";
> +       };
> +
> +       cpus {
> +               timebase-frequency = <RTCCLK_FREQ>;
> +       };
> +
> +       memory@80000000 {
> +               device_type = "memory";
> +               reg = <0x0 0x80000000 0x4 0x00000000>;
> +       };
> +
> +       soc {
> +       };
> +
> +       hfclk: hfclk {
> +               #clock-cells = <0>;
> +               compatible = "fixed-clock";
> +               clock-frequency = <26000000>;
> +               clock-output-names = "hfclk";
> +       };
> +
> +       rtcclk: rtcclk {
> +               #clock-cells = <0>;
> +               compatible = "fixed-clock";
> +               clock-frequency = <RTCCLK_FREQ>;
> +               clock-output-names = "rtcclk";
> +       };
> +};
> +
> +&uart0 {
> +       status = "okay";
> +};
> +
> +&uart1 {
> +       status = "okay";
> +};
> +

> +
> +&qspi0 {
> +       status = "okay";
> +       flash@0 {
> +               compatible = "issi,is25wp256", "jedec,spi-nor";
> +               reg = <0>;
> +               spi-max-frequency = <50000000>;
> +               m25p,fast-read;
> +               spi-tx-bus-width = <4>;
> +               spi-rx-bus-width = <4>;
> +       };
> +};
> +
> +&spi0 {
> +       status = "okay";
> +       mmc@0 {
> +               compatible = "mmc-spi-slot";
> +               reg = <0>;
> +               spi-max-frequency = <20000000>;
> +               voltage-ranges = <3300 3300>;
> +               disable-wp;
> +       };
> +};
> +
> +&eth0 {
> +       status = "okay";
> +       phy-mode = "gmii";
> +       phy-handle = <&phy0>;
> +       phy0: ethernet-phy@0 {
> +               reg = <0>;
> +       };
> +};
> +
> +&pwm0 {
> +       status = "okay";
> +};
> +
> +&pwm1 {
> +       status = "okay";
> +};
> +
> +&gpio {
> +       status = "okay";
> +};
> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
> index 64fdbd4..e70d1e5 100644
> --- a/board/sifive/fu540/Kconfig
> +++ b/board/sifive/fu540/Kconfig
> @@ -47,6 +47,5 @@ config BOARD_SPECIFIC_OPTIONS # dummy
>         imply SPI_FLASH_ISSI
>         imply SYSRESET
>         imply SYSRESET_GPIO
> -       imply CMD_I2C
>
>  endif
> diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
> index a4e7822..54e5a4c 100644
> --- a/board/sifive/fu540/fu540.c
> +++ b/board/sifive/fu540/fu540.c
> @@ -58,7 +58,7 @@ static u32 fu540_read_serialnum(void)
>
>         /* init OTP */
>         ret = uclass_get_device_by_driver(UCLASS_MISC,
> -                                         DM_DRIVER_GET(sifive_otp), &dev);
> +                                         DM_GET_DRIVER(sifive_otp), &dev);
>
>         if (ret) {
>                 debug("%s: could not find otp device\n", __func__);
> diff --git a/board/sifive/hifive_unmatched_fu740/Kconfig b/board/sifive/hifive_unmatched_fu740/Kconfig
> new file mode 100644
> index 0000000..53c87c6
> --- /dev/null
> +++ b/board/sifive/hifive_unmatched_fu740/Kconfig
> @@ -0,0 +1,50 @@
> +if TARGET_SIFIVE_UNMATCHED
> +
> +config SYS_BOARD
> +       default "hifive_unmatched_fu740"
> +
> +config SYS_VENDOR
> +       default "sifive"
> +
> +config SYS_CPU
> +       default "fu740"
> +
> +config SYS_CONFIG_NAME
> +       default "sifive-hifive-unmatched-fu740"
> +
> +config SYS_TEXT_BASE
> +       default 0x80200000 if SPL
> +       default 0x80000000 if !RISCV_SMODE
> +       default 0x80200000 if RISCV_SMODE
> +
> +config SPL_TEXT_BASE
> +       default 0x08000000
> +
> +config SPL_OPENSBI_LOAD_ADDR
> +       default 0x80000000
> +
> +config BOARD_SPECIFIC_OPTIONS # dummy
> +       def_bool y
> +       select SIFIVE_FU740
> +       select SUPPORT_SPL
> +       select RESET_SIFIVE
> +       imply CMD_DHCP
> +       imply CMD_EXT2
> +       imply CMD_EXT4
> +       imply CMD_FAT
> +       imply CMD_FS_GENERIC
> +       imply CMD_GPT
> +       imply PARTITION_TYPE_GUID
> +       imply CMD_NET
> +       imply CMD_PING
> +       imply CMD_SF
> +       imply DOS_PARTITION
> +       imply EFI_PARTITION
> +       imply IP_DYN
> +       imply ISO_PARTITION
> +       imply PHY_LIB
> +       imply PHY_MSCC
> +       imply SYSRESET
> +       imply SYSRESET_GPIO
> +
> +endif
> diff --git a/board/sifive/hifive_unmatched_fu740/MAINTAINERS b/board/sifive/hifive_unmatched_fu740/MAINTAINERS
> new file mode 100644
> index 0000000..783b20d
> --- /dev/null
> +++ b/board/sifive/hifive_unmatched_fu740/MAINTAINERS
> @@ -0,0 +1,9 @@
> +SiFive HiFive Unmatched FU740 BOARD
> +M:     Paul Walmsley <paul.walmsley@sifive.com>
> +M:     Pragnesh Patel <pragnesh.patel@sifive.com>
> +M:     Green Wan <green.wan@sifive.com>
> +S:     Maintained
> +F:     board/sifive/hifive_unmatched_fu740/
> +F:     doc/board/sifive/hifive-unmatched-fu740.rst
> +F:     include/configs/sifive-hifive-unmatched-fu740.h
> +F:     configs/sifive_hifive_unmatched_fu740_defconfig
> diff --git a/board/sifive/hifive_unmatched_fu740/Makefile b/board/sifive/hifive_unmatched_fu740/Makefile
> new file mode 100644
> index 0000000..aeab025
> --- /dev/null
> +++ b/board/sifive/hifive_unmatched_fu740/Makefile
> @@ -0,0 +1,9 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (c) 2020 SiFive, Inc
> +
> +obj-y   += hifive-unmatched-fu740.o
> +
> +ifdef CONFIG_SPL_BUILD
> +obj-y += spl.o
> +endif
> diff --git a/board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c b/board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c
> new file mode 100644
> index 0000000..361bfbf
> --- /dev/null
> +++ b/board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c
> @@ -0,0 +1,24 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2020, SiFive Inc
> + *
> + * Authors:
> + *   Pragnesh Patel <pragnesh.patel@sifive.com>
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <asm/arch/cache.h>
> +
> +int board_init(void)
> +{
> +       int ret;
> +
> +       /* enable all cache ways */
> +       ret = cache_enable_ways();
> +       if (ret) {
> +               debug("%s: could not enable cache ways\n", __func__);
> +               return ret;
> +       }
> +       return 0;
> +}
> diff --git a/board/sifive/hifive_unmatched_fu740/spl.c b/board/sifive/hifive_unmatched_fu740/spl.c
> new file mode 100644
> index 0000000..d8ee934
> --- /dev/null
> +++ b/board/sifive/hifive_unmatched_fu740/spl.c
> @@ -0,0 +1,85 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (c) 2020 SiFive, Inc
> + *
> + * Authors:
> + *   Pragnesh Patel <pragnesh.patel@sifive.com>
> + */
> +
> +#include <init.h>
> +#include <spl.h>
> +#include <misc.h>
> +#include <log.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <asm/gpio.h>
> +#include <asm/arch/gpio.h>
> +#include <asm/arch/spl.h>
> +
> +#define GEM_PHY_RESET  SIFIVE_GENERIC_GPIO_NR(0, 12)
> +
> +#define MODE_SELECT_REG                0x1000
> +#define MODE_SELECT_SD         0xb
> +#define MODE_SELECT_MASK       GENMASK(3, 0)
> +
> +int spl_board_init_f(void)
> +{
> +       int ret;
> +
> +       ret = spl_soc_init();
> +       if (ret) {
> +               debug("HiFive Unmatched FU740 SPL init failed: %d\n", ret);
> +               return ret;
> +       }
> +
> +       /*
> +        * GEMGXL init VSC8541 PHY reset sequence;
> +        * leave pull-down active for 2ms
> +        */
> +       udelay(2000);
> +       ret = gpio_request(GEM_PHY_RESET, "gem_phy_reset");
> +       if (ret) {
> +               debug("gem_phy_reset gpio request failed: %d\n", ret);
> +               return ret;
> +       }
> +
> +       /* Set GPIO 12 (PHY NRESET) */
> +       ret = gpio_direction_output(GEM_PHY_RESET, 1);
> +       if (ret) {
> +               debug("gem_phy_reset gpio direction set failed: %d\n", ret);
> +               return ret;
> +       }
> +
> +       udelay(1);
> +
> +       /* Reset PHY again to enter unmanaged mode */
> +       gpio_set_value(GEM_PHY_RESET, 0);
> +       udelay(1);
> +       gpio_set_value(GEM_PHY_RESET, 1);
> +       mdelay(15);
> +
> +       return 0;
> +}
> +
> +u32 spl_boot_device(void)
> +{
> +       u32 mode_select = readl((void *)MODE_SELECT_REG);
> +       u32 boot_device = mode_select & MODE_SELECT_MASK;
> +
> +       switch (boot_device) {
> +       case MODE_SELECT_SD:
> +               return BOOT_DEVICE_MMC1;

No booting from SPI flash support?

> +       default:
> +               debug("Unsupported boot device 0x%x but trying MMC1\n",
> +                     boot_device);
> +               return BOOT_DEVICE_MMC1;
> +       }
> +}
> +
> +#ifdef CONFIG_SPL_LOAD_FIT
> +int board_fit_config_name_match(const char *name)
> +{
> +       /* boot using first FIT config */
> +       return 0;
> +}
> +#endif
> diff --git a/configs/sifive_hifive_unmatched_fu740_defconfig b/configs/sifive_hifive_unmatched_fu740_defconfig
> new file mode 100644
> index 0000000..5ec1ee6
> --- /dev/null
> +++ b/configs/sifive_hifive_unmatched_fu740_defconfig
> @@ -0,0 +1,57 @@
> +CONFIG_RISCV=y
> +CONFIG_SPL_GPIO_SUPPORT=y
> +CONFIG_SYS_MALLOC_F_LEN=0x3000
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_SPL_DM_SPI=y
> +CONFIG_SPL_MMC_SUPPORT=y
> +CONFIG_SPL=y
> +CONFIG_SPL_SPI_SUPPORT=y
> +CONFIG_DEFAULT_DEVICE_TREE="hifive-unmatched-a00"
> +CONFIG_TARGET_SIFIVE_UNMATCHED=y
> +CONFIG_ARCH_RV64I=y
> +CONFIG_RISCV_SMODE=y
> +CONFIG_DISTRO_DEFAULTS=y
> +CONFIG_FIT=y
> +CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
> +CONFIG_DISPLAY_CPUINFO=y
> +CONFIG_DISPLAY_BOARDINFO=y
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
> +CONFIG_SPL_SEPARATE_BSS=y
> +CONFIG_SPL_DM_RESET=y
> +CONFIG_SPL_YMODEM_SUPPORT=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_SPL_CLK=y
> +CONFIG_DM_RESET=y
> +CONFIG_CMD_PCI=y
> +CONFIG_PCI=y
> +CONFIG_DM_PCI=y
> +CONFIG_PCI_PNP=y
> +CONFIG_PCIE_SIFIVE_FU740=y
> +CONFIG_NVME=y
> +CONFIG_DM_ETH=y
> +CONFIG_NETDEVICES=y
> +CONFIG_E1000=y
> +CONFIG_USB=y
> +CONFIG_CMD_USB=y
> +CONFIG_DM_USB=y
> +CONFIG_USB_STORAGE=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_XHCI_PCI=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_EHCI_GENERIC=y
> +CONFIG_USB_OHCI_HCD=y
> +CONFIG_USB_OHCI_GENERIC=y
> +CONFIG_CMD_PART=y
> +CONFIG_CMD_NVME=y
> +CONFIG_SYS_USB_EVENT_POLL=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_GPT_RENAME=y
> +CONFIG_CMD_EEPROM=y
> +CONFIG_CMD_MEMINFO=y
> +CONFIG_CMD_I2C=y
> +CONFIG_DM_I2C=y
> +CONFIG_SYS_I2C_OCORES=y
> +CONFIG_CLK_SIFIVE_PRCI=y
> +ONFIG_DM_PWM=y
> +CONFIG_PWM_SIFIVE=y
> +CONFIG_CMD_PWM=y
> diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst
> index 4e4c852..1ce9ab1 100644
> --- a/doc/board/sifive/fu540.rst
> +++ b/doc/board/sifive/fu540.rst
> @@ -12,7 +12,6 @@ of running Linux.
>
>  Mainline support
>  ----------------
> -
>  The support for following drivers are already enabled:
>
>  1. SiFive UART Driver.
> @@ -25,7 +24,7 @@ Booting from MMC using FSBL
>  ---------------------------
>
>  Building
> -~~~~~~~~
> +--------
>
>  1. Add the RISC-V toolchain to your PATH.
>  2. Setup ARCH & cross compilation environment variable:
> @@ -38,7 +37,7 @@ Building
>  4. make
>
>  Flashing
> -~~~~~~~~
> +--------
>
>  The current U-Boot port is supported in S-mode only and loaded from DRAM.
>
> @@ -64,12 +63,11 @@ copied to the first partition of the sdcard.
>      sudo dd if=<prior_stage_firmware_binary> of=/dev/disk2s1 bs=1024
>
>  Booting
> -~~~~~~~
> -
> +-------
>  Once you plugin the sdcard and power up, you should see the U-Boot prompt.
>
>  Sample boot log from HiFive Unleashed board
> -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> +-------------------------------------------
>
>  .. code-block:: none
>
> @@ -419,7 +417,7 @@ Booting from MMC using U-Boot SPL
>  ---------------------------------
>
>  Building
> -~~~~~~~~
> +--------
>
>  Before building U-Boot SPL, OpenSBI must be built first. OpenSBI can be
>  cloned and built for FU540 as below:
> @@ -443,7 +441,7 @@ This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
>
>
>  Flashing
> -~~~~~~~~
> +--------
>
>  ZSBL loads the U-Boot SPL (u-boot-spl.bin) from a partition with GUID type
>  5B193300-FC78-40CD-8002-E86C45580B47
> @@ -473,12 +471,11 @@ Program the SD card
>         sudo dd if=u-boot.itb of=/dev/sda seek=2082
>
>  Booting
> -~~~~~~~
> -
> +-------
>  Once you plugin the sdcard and power up, you should see the U-Boot prompt.
>
>  Sample boot log from HiFive Unleashed board
> -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> +-------------------------------------------
>
>  .. code-block:: none
>
> diff --git a/doc/board/sifive/hifive_unmatched_fu740.rst b/doc/board/sifive/hifive_unmatched_fu740.rst
> new file mode 100644
> index 0000000..6670df5
> --- /dev/null
> +++ b/doc/board/sifive/hifive_unmatched_fu740.rst
> @@ -0,0 +1,532 @@
> +.. SPDX-License-Identifier: GPL-2.0+
> +
> +HiFive Unmatched
> +================
> +
> +FU740-C000 RISC-V SoC
> +---------------------
> +The FU740-C000 is a 4+1 64-bit RISC-V core SoC from SiFive.
> +
> +The HiFive Unmatched development platform is based on FU740-C000 and capable
> +of running Linux.
> +
> +Mainline support
> +----------------
> +The support for following drivers are already enabled:
> +
> +1. SiFive UART Driver.
> +2. SiFive PRCI Driver for clock.
> +3. Cadence MACB ethernet driver for networking support.
> +4. SiFive SPI Driver.
> +5. MMC SPI Driver for MMC/SD support.
> +
> +Booting from MMC using u-boot-spl
> +---------------------------
> +
> +Building
> +--------
> +
> +1. Add the RISC-V toolchain to your PATH.
> +2. Setup ARCH & cross compilation environment variable:
> +
> +.. code-block:: none
> +
> +   export CROSS_COMPILE=<riscv64 toolchain prefix>
> +
> +3. make sifive_hifive_unmatched_fu740_defconfig
> +4. make
> +
> +Flashing
> +--------
> +
> +The current U-Boot port is supported in S-mode only and loaded from DRAM.
> +
> +A prior stage M-mode firmware/bootloader (e.g OpenSBI) is required to
> +boot the u-boot.bin in S-mode and provide M-mode runtime services.
> +
> +Currently, the u-boot.bin is used as a payload of the OpenSBI FW_PAYLOAD
> +firmware. We need to compile OpenSBI with below command:
> +
> +.. code-block:: none
> +
> +       make PLATFORM=generic FW_PAYLOAD_PATH=<path to u-boot-dtb.bin>
> +
> +More detailed description of steps required to build FW_PAYLOAD firmware
> +is beyond the scope of this document. Please refer OpenSBI documenation.
> +(Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git)
> +
> +Once the prior stage firmware/bootloader binary is generated, it should be
> +copied to the first partition of the sdcard.
> +
> +.. code-block:: none
> +
> +    sudo dd if=<prior_stage_firmware_binary> of=/dev/disk2s1 bs=1024
> +
> +Booting
> +-------
> +Once you plugin the sdcard and power up, you should see the U-Boot prompt.
> +
> +Sample boot log from HiFive Unmatched board
> +-------------------------------------------
> +
> +.. code-block:: none
> +
> +   U-Boot 2019.07-00024-g350ff02f5b (Jul 22 2019 - 11:45:02 +0530)

This seems to be pretty old U-Boot

> +
> +   CPU:   rv64imafdc
> +   Model: SiFive HiFive Unmatched A00
> +   DRAM:  8 GiB
> +   MMC:   spi@10050000:mmc@0: 0
> +   In:    serial@10010000
> +   Out:   serial@10010000
> +   Err:   serial@10010000
> +   Net:   eth0: ethernet@10090000
> +   Hit any key to stop autoboot:  0
> +   => version
> +   U-Boot 2019.07-00024-g350ff02f5b (Jul 22 2019 - 11:45:02 +0530)
> +
> +   riscv64-linux-gcc.br_real (Buildroot 2018.11-rc2-00003-ga0787e9) 8.2.0
> +   GNU ld (GNU Binutils) 2.31.1
> +   => mmc info
> +   Device: spi@10050000:mmc@0
> +   Manufacturer ID: 3
> +   OEM: 5344
> +   Name: SU08G
> +   Bus Speed: 20000000
> +   Mode: SD Legacy
> +   Rd Block Len: 512
> +   SD version 2.0
> +   High Capacity: Yes
> +   Capacity: 7.4 GiB
> +   Bus Width: 1-bit
> +   Erase Group Size: 512 Bytes
> +   => mmc part
> +
> +   Partition Map for MMC device 0  --   Partition Type: EFI
> +
> +   Part    Start LBA       End LBA         Name
> +           Attributes
> +           Type GUID
> +           Partition GUID
> +     1     0x00000800      0x000107ff      "bootloader"
> +           attrs:  0x0000000000000000
> +           type:   2e54b353-1271-4842-806f-e436d6af6985
> +           guid:   393bbd36-7111-491c-9869-ce24008f6403
> +     2     0x00040800      0x00ecdfde      ""
> +           attrs:  0x0000000000000000
> +           type:   0fc63daf-8483-4772-8e79-3d69d8477de4
> +           guid:   7fc9a949-5480-48c7-b623-04923080757f
> +
> +Now you can configure your networking, tftp server and use tftp boot method to
> +load uImage.
> +
> +.. code-block:: none
> +
> +   => setenv ipaddr 10.206.7.133
> +   => setenv netmask 255.255.252.0
> +   => setenv serverip 10.206.4.143
> +   => setenv gateway 10.206.4.1
> +
> +If you want to use a flat kernel image such as Image file
> +
> +.. code-block:: none
> +
> +   => tftpboot ${kernel_addr_r} /sifive/fu740/Image
> +   ethernet@10090000: PHY present at 0
> +   ethernet@10090000: Starting autonegotiation...
> +   ethernet@10090000: Autonegotiation complete
> +   ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3c00)
> +   Using ethernet@10090000 device
> +   TFTP from server 10.206.4.143; our IP address is 10.206.7.133
> +   Filename '/sifive/fu740/Image'.
> +   Load address: 0x84000000
> +   Loading: #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            ##########################################
> +            1.2 MiB/s
> +   done
> +   Bytes transferred = 8867100 (874d1c hex)
> +
> +Or if you want to use a compressed kernel image file such as Image.gz
> +
> +.. code-block:: none
> +
> +   => tftpboot ${kernel_addr_r} /sifive/fu740/Image.gz
> +   ethernet@10090000: PHY present at 0
> +   ethernet@10090000: Starting autonegotiation...
> +   ethernet@10090000: Autonegotiation complete
> +   ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3c00)
> +   Using ethernet@10090000 device
> +   TFTP from server 10.206.4.143; our IP address is 10.206.7.133
> +   Filename '/sifive/fu740/Image.gz'.
> +   Load address: 0x84000000
> +   Loading: #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            ##########################################
> +            1.2 MiB/s
> +   done
> +   Bytes transferred = 4809458 (4962f2 hex)
> +   =>setenv kernel_comp_addr_r 0x90000000
> +   =>setenv kernel_comp_size 0x500000
> +
> +By this time, correct kernel image is loaded and required environment variables
> +are set. You can proceed to load the ramdisk and device tree from the tftp server
> +as well.
> +
> +.. code-block:: none
> +
> +   => tftpboot ${ramdisk_addr_r} /sifive/fu740/uRamdisk
> +   ethernet@10090000: PHY present at 0
> +   ethernet@10090000: Starting autonegotiation...
> +   ethernet@10090000: Autonegotiation complete
> +   ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3c00)
> +   Using ethernet@10090000 device
> +   TFTP from server 10.206.4.143; our IP address is 10.206.7.133
> +   Filename '/sifive/fu740/uRamdisk'.
> +   Load address: 0x88300000
> +   Loading: #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            #################################################################
> +            ##############
> +            418.9 KiB/s
> +   done
> +   Bytes transferred = 2398272 (249840 hex)
> +   => tftpboot ${fdt_addr_r} /sifive/fu740/hifive-unmatched-a00.dtb
> +   ethernet@10090000: PHY present at 0
> +   ethernet@10090000: Starting autonegotiation...
> +   ethernet@10090000: Autonegotiation complete
> +   ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x7c00)
> +   Using ethernet@10090000 device
> +   TFTP from server 10.206.4.143; our IP address is 10.206.7.133
> +   Filename '/sifive/fu740/hifive-unmatched-a00.dtb'.
> +   Load address: 0x88000000
> +   Loading: ##
> +            1000 Bytes/s
> +   done
> +   Bytes transferred = 5614 (15ee hex)
> +   => setenv bootargs "root=/dev/ram rw console=ttySIF0 ip=dhcp earlycon=sbi"
> +   => booti ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}
> +   ## Loading init Ramdisk from Legacy Image at 88300000 ...
> +      Image Name:   Linux RootFS
> +      Image Type:   RISC-V Linux RAMDisk Image (uncompressed)
> +      Data Size:    2398208 Bytes = 2.3 MiB
> +      Load Address: 00000000
> +      Entry Point:  00000000
> +      Verifying Checksum ... OK
> +   ## Flattened Device Tree blob at 88000000
> +      Booting using the fdt blob at 0x88000000
> +      Using Device Tree in place at 0000000088000000, end 00000000880045ed
> +
> +   Starting kernel ...
> +
> +   [    0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000
> +   [    0.000000] Linux version 5.3.0-rc1-00003-g460ac558152f (anup@anup-lab-machine) (gcc version 8.2.0 (Buildroot 2018.11-rc2-00003-ga0787e9)) #6 SMP Mon Jul 22 10:01:01 IST 2019

Looks this is an old kernel used for testing? I doubt it contains the
new fu740-prci driver and PCIe support.

> +   [    0.000000] earlycon: sbi0 at I/O port 0x0 (options '')
> +   [    0.000000] printk: bootconsole [sbi0] enabled
> +   [    0.000000] Initial ramdisk at: 0x(____ptrval____) (2398208 bytes)
> +   [    0.000000] Zone ranges:
> +   [    0.000000]   DMA32    [mem 0x0000000080200000-0x00000000ffffffff]
> +   [    0.000000]   Normal   [mem 0x0000000100000000-0x000000027fffffff]
> +   [    0.000000] Movable zone start for each node
> +   [    0.000000] Early memory node ranges
> +   [    0.000000]   node   0: [mem 0x0000000080200000-0x000000027fffffff]
> +   [    0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x000000027fffffff]
> +   [    0.000000] software IO TLB: mapped [mem 0xfbfff000-0xfffff000] (64MB)
> +   [    0.000000] CPU with hartid=0 is not available
> +   [    0.000000] CPU with hartid=0 is not available
> +   [    0.000000] elf_hwcap is 0x112d
> +   [    0.000000] percpu: Embedded 18 pages/cpu s34584 r8192 d30952 u73728
> +   [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2067975
> +   [    0.000000] Kernel command line: root=/dev/ram rw console=ttySIF0 ip=dhcp earlycon=sbi
> +   [    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
> +   [    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
> +   [    0.000000] Sorting __ex_table...
> +   [    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
> +   [    0.000000] Memory: 8182308K/8386560K available (5916K kernel code, 368K rwdata, 1840K rodata, 213K init, 304K bss, 204252K reserved, 0K cma-reserved)
> +   [    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
> +   [    0.000000] rcu: Hierarchical RCU implementation.
> +   [    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
> +   [    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
> +   [    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
> +   [    0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
> +   [    0.000000] plic: mapped 53 interrupts with 4 handlers for 9 contexts.
> +   [    0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [1]
> +   [    0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns
> +   [    0.000006] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns
> +   [    0.008559] Console: colour dummy device 80x25
> +   [    0.012989] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=4000)
> +   [    0.023104] pid_max: default: 32768 minimum: 301
> +   [    0.028273] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
> +   [    0.035765] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
> +   [    0.045307] rcu: Hierarchical SRCU implementation.
> +   [    0.049875] smp: Bringing up secondary CPUs ...
> +   [    0.055729] smp: Brought up 1 node, 4 CPUs
> +   [    0.060599] devtmpfs: initialized
> +   [    0.064819] random: get_random_u32 called from bucket_table_alloc.isra.10+0x4e/0x160 with crng_init=0
> +   [    0.073720] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
> +   [    0.083176] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
> +   [    0.090721] NET: Registered protocol family 16
> +   [    0.106319] vgaarb: loaded
> +   [    0.108670] SCSI subsystem initialized
> +   [    0.112515] usbcore: registered new interface driver usbfs
> +   [    0.117758] usbcore: registered new interface driver hub
> +   [    0.123167] usbcore: registered new device driver usb
> +   [    0.128905] clocksource: Switched to clocksource riscv_clocksource
> +   [    0.141239] NET: Registered protocol family 2
> +   [    0.145506] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
> +   [    0.153754] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
> +   [    0.163466] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes, linear)
> +   [    0.173468] TCP: Hash tables configured (established 65536 bind 65536)
> +   [    0.179739] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
> +   [    0.186627] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
> +   [    0.194117] NET: Registered protocol family 1
> +   [    0.198417] RPC: Registered named UNIX socket transport module.
> +   [    0.203887] RPC: Registered udp transport module.
> +   [    0.208664] RPC: Registered tcp transport module.
> +   [    0.213429] RPC: Registered tcp NFSv4.1 backchannel transport module.
> +   [    0.219944] PCI: CLS 0 bytes, default 64
> +   [    0.224170] Unpacking initramfs...
> +   [    0.262347] Freeing initrd memory: 2336K
> +   [    0.266531] workingset: timestamp_bits=62 max_order=21 bucket_order=0
> +   [    0.280406] NFS: Registering the id_resolver key type
> +   [    0.284798] Key type id_resolver registered
> +   [    0.289048] Key type id_legacy registered
> +   [    0.293114] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
> +   [    0.300262] NET: Registered protocol family 38
> +   [    0.304432] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
> +   [    0.311862] io scheduler mq-deadline registered
> +   [    0.316461] io scheduler kyber registered
> +   [    0.356421] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
> +   [    0.363004] 10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 4, base_baud = 0) is a SiFive UART v0
> +   [    0.371468] printk: console [ttySIF0] enabled
> +   [    0.371468] printk: console [ttySIF0] enabled
> +   [    0.380223] printk: bootconsole [sbi0] disabled
> +   [    0.380223] printk: bootconsole [sbi0] disabled
> +   [    0.389589] 10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 1, base_baud = 0) is a SiFive UART v0
> +   [    0.398680] [drm] radeon kernel modesetting enabled.
> +   [    0.412395] loop: module loaded
> +   [    0.415214] sifive_spi 10040000.spi: mapped; irq=3, cs=1
> +   [    0.420628] sifive_spi 10050000.spi: mapped; irq=5, cs=1
> +   [    0.425897] libphy: Fixed MDIO Bus: probed
> +   [    0.429964] macb 10090000.ethernet: Registered clk switch 'sifive-gemgxl-mgmt'
> +   [    0.436743] macb: GEM doesn't support hardware ptp.
> +   [    0.441621] libphy: MACB_mii_bus: probed
> +   [    0.601316] Microsemi VSC8541 SyncE 10090000.ethernet-ffffffff:00: attached PHY driver [Microsemi VSC8541 SyncE] (mii_bus:phy_addr=10090000.ethernet-ffffffff:00, irq=POLL)
> +   [    0.615857] macb 10090000.ethernet eth0: Cadence GEM rev 0x10070109 at 0x10090000 irq 6 (70:b3:d5:92:f2:f3)
> +   [    0.625634] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
> +   [    0.631381] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
> +   [    0.637382] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
> +   [    0.643799] ehci-pci: EHCI PCI platform driver
> +   [    0.648261] ehci-platform: EHCI generic platform driver
> +   [    0.653497] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
> +   [    0.659599] ohci-pci: OHCI PCI platform driver
> +   [    0.664055] ohci-platform: OHCI generic platform driver
> +   [    0.669448] usbcore: registered new interface driver uas
> +   [    0.674575] usbcore: registered new interface driver usb-storage
> +   [    0.680642] mousedev: PS/2 mouse device common for all mice
> +   [    0.709493] mmc_spi spi1.0: SD/MMC host mmc0, no DMA, no WP, no poweroff, cd polling
> +   [    0.716615] usbcore: registered new interface driver usbhid
> +   [    0.722023] usbhid: USB HID core driver
> +   [    0.726738] NET: Registered protocol family 10
> +   [    0.731359] Segment Routing with IPv6
> +   [    0.734332] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
> +   [    0.740687] NET: Registered protocol family 17
> +   [    0.744660] Key type dns_resolver registered
> +   [    0.806775] mmc0: host does not support reading read-only switch, assuming write-enable
> +   [    0.814020] mmc0: new SDHC card on SPI
> +   [    0.820137] mmcblk0: mmc0:0000 SU08G 7.40 GiB
> +   [    0.850220]  mmcblk0: p1 p2
> +   [    3.821524] macb 10090000.ethernet eth0: link up (1000/Full)
> +   [    3.828938] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
> +   [    3.848919] Sending DHCP requests .., OK
> +   [    6.252076] IP-Config: Got DHCP answer from 10.206.4.1, my address is 10.206.7.133
> +   [    6.259624] IP-Config: Complete:
> +   [    6.262831]      device=eth0, hwaddr=70:b3:d5:92:f2:f3, ipaddr=10.206.7.133, mask=255.255.252.0, gw=10.206.4.1
> +   [    6.272809]      host=dhcp-10-206-7-133, domain=sdcorp.global.sandisk.com, nis-domain=(none)
> +   [    6.281228]      bootserver=10.206.126.11, rootserver=10.206.126.11, rootpath=
> +   [    6.281232]      nameserver0=10.86.1.1, nameserver1=10.86.2.1
> +   [    6.294179]      ntpserver0=10.86.1.1, ntpserver1=10.86.2.1
> +   [    6.301026] Freeing unused kernel memory: 212K
> +   [    6.304683] This architecture does not have kernel memory protection.
> +   [    6.311121] Run /init as init process
> +              _  _
> +             | ||_|
> +             | | _ ____  _   _  _  _
> +             | || |  _ \| | | |\ \/ /
> +             | || | | | | |_| |/    \
> +             |_||_|_| |_|\____|\_/\_/
> +
> +                  Busybox Rootfs
> +
> +   Please press Enter to activate this console.
> +   / #
> +
> +Booting from MMC using U-Boot SPL
> +---------------------------------
> +
> +Building
> +--------
> +
> +Before building U-Boot SPL, OpenSBI must be built first. OpenSBI can be
> +cloned and built for FU740 as below:
> +
> +.. code-block:: console
> +
> +       git clone https://github.com/riscv/opensbi.git
> +       cd opensbi
> +       make PLATFORM=generic
> +       export OPENSBI=<path to opensbi/build/platform/generic/firmware/fw_dynamic.bin>
> +
> +Now build the U-Boot SPL and U-Boot proper
> +
> +.. code-block:: console
> +
> +       cd <U-Boot-dir>
> +       make sifive_hifive_unmatched_fu740_defconfig
> +       make
> +
> +This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
> +
> +
> +Flashing
> +--------
> +
> +ZSBL loads the U-Boot SPL (u-boot-spl.bin) from a partition with GUID type
> +5B193300-FC78-40CD-8002-E86C45580B47
> +
> +U-Boot SPL expects a U-Boot FIT image (u-boot.itb) from a partition with GUID
> +type 2E54B353-1271-4842-806F-E436D6AF6985
> +
> +FIT image (u-boot.itb) is a combination of fw_dynamic.bin, u-boot-nodtb.bin and
> +device tree blob (hifive-unmatched-a00.dtb)
> +
> +Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch)
> +
> +.. code-block:: none
> +
> +       # sudo sgdisk --clear \
> +       > --set-alignment=2 \
> +       > --new=1:34:2081 --change-name=1:loader1 --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \
> +       > --new=2:2082:10273 --change-name=2:loader2 --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \
> +       > --new=3:10274: --change-name=3:rootfs --typecode=3:0FC63DAF-8483-4772-8E79-3D69D8477DE4 \
> +       > /dev/sda
> +
> +Program the SD card
> +
> +.. code-block:: none
> +
> +       sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34
> +       sudo dd if=u-boot.itb of=/dev/sda seek=2082
> +
> +Booting
> +-------
> +Once you plugin the sdcard and power up, you should see the U-Boot prompt.
> +
> +Sample boot log from HiFive Unmatched board
> +-------------------------------------------
> +
> +.. code-block:: none
> +
> +        U-Boot SPL 2021.04-rc3 (Mar 11 2021 - 08:07:46 +0000)
> +        Trying to boot from MMC1
> +
> +
> +        U-Boot 2021.04-rc3 (Mar 11 2021 - 08:07:46 +0000)
> +
> +        CPU:   rv64imafdc
> +        Model: SiFive HiFive Unmatched A00
> +        DRAM:  16 GiB
> +        MMC:   spi@10050000:mmc@0: 0
> +        In:    serial@10010000
> +        Out:   serial@10010000
> +        Err:   serial@10010000
> +        Model: SiFive HiFive Unmatched A00
> +        Net:
> +        Error: ethernet@10090000 address not set.
> +        No ethernet found.
> +
> +        Hit any key to stop autoboot:  0
> +        => version
> +        U-Boot 2021.04-rc3 (Mar 11 2021 - 08:07:46 +0000)
> +
> +        riscv64-oe-linux-gcc (GCC) 10.2.0
> +        GNU ld (GNU Binutils) 2.35.0.20200730
> +        => mmc part
> +
> +        Partition Map for MMC device 0  --   Partition Type: EFI
> +
> +        Part    Start LBA       End LBA         Name
> +        Attributes
> +        Type GUID
> +        Partition GUID
> +        1     0x00000022      0x00000821      "primary"
> +              attrs:  0x0000000000000000
> +              type:   5b193300-fc78-40cd-8002-e86c45580b47
> +              guid:   f4b7c671-63ec-4f3b-8f26-3f10407df3c7
> +        2     0x00000822      0x00002821      "primary"
> +              attrs:  0x0000000000000000
> +              type:   2e54b353-1271-4842-806f-e436d6af6985
> +              guid:   e48d9a09-ff68-4219-abb4-62917290de3c
> +        3     0x00004000      0x00044fff      "boot"
> +              attrs:  0x0000000000000004
> +              type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> +              type:   data
> +              guid:   6af708a6-0e40-4476-a900-cd59954034f1
> +        4     0x00046000      0x03b723de      "root"
> +              attrs:  0x0000000000000000
> +              type:   0fc63daf-8483-4772-8e79-3d69d8477de4
> +              type:   linux
> +              guid:   038165a5-b704-4d96-9bc4-2533803c6620
> +
> diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> index f5b3f88..33bbbd5 100644
> --- a/drivers/reset/Kconfig
> +++ b/drivers/reset/Kconfig
> @@ -166,7 +166,7 @@ config RESET_IPQ419
>
>  config RESET_SIFIVE
>         bool "Reset Driver for SiFive SoC's"
> -       depends on DM_RESET && CLK_SIFIVE_FU540_PRCI && TARGET_SIFIVE_FU540
> +       depends on DM_RESET && CLK_SIFIVE_PRCI && (TARGET_SIFIVE_FU540 || TARGET_SIFIVE_HIFIVE_UNMATCHED_FU740)
>         default y
>         help
>           PRCI module within SiFive SoC's provides mechanism to reset
> diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
> index 0d69d1c..c1c79db 100644
> --- a/include/configs/sifive-fu540.h
> +++ b/include/configs/sifive-fu540.h
> @@ -36,11 +36,6 @@
>
>  #define CONFIG_STANDALONE_LOAD_ADDR    0x80200000
>
> -#define RISCV_MMODE_TIMERBASE          0x2000000
> -#define RISCV_MMODE_TIMER_FREQ         1000000
> -
> -#define RISCV_SMODE_TIMER_FREQ         1000000
> -

These changes seem not needed?

>  /* Environment options */
>
>  #ifndef CONFIG_SPL_BUILD
> diff --git a/include/configs/sifive-hifive-unmatched-fu740.h b/include/configs/sifive-hifive-unmatched-fu740.h
> new file mode 100644
> index 0000000..b59df9c
> --- /dev/null
> +++ b/include/configs/sifive-hifive-unmatched-fu740.h
> @@ -0,0 +1,88 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2020 SiFive, Inc
> + *
> + * Authors:
> + *   Pragnesh Patel <pragnesh.patel@sifive.com>
> + */
> +
> +#ifndef __SIFIVE_UNMATCHED_H
> +#define __SIFIVE_UNMATCHED_H
> +
> +#include <linux/sizes.h>
> +
> +#ifdef CONFIG_SPL
> +
> +#define CONFIG_SPL_MAX_SIZE            0x00100000
> +#define CONFIG_SPL_BSS_START_ADDR      0x85000000
> +#define CONFIG_SPL_BSS_MAX_SIZE                0x00100000
> +#define CONFIG_SYS_SPL_MALLOC_START    (CONFIG_SPL_BSS_START_ADDR + \
> +                                        CONFIG_SPL_BSS_MAX_SIZE)
> +#define CONFIG_SYS_SPL_MALLOC_SIZE     0x00100000
> +
> +#define CONFIG_SPL_STACK       (0x08000000 + 0x001D0000 - \
> +                                GENERATED_GBL_DATA_SIZE)
> +
> +#endif
> +
> +#define CONFIG_SYS_SDRAM_BASE          0x80000000
> +#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_SDRAM_BASE + SZ_2M)
> +
> +#define CONFIG_SYS_LOAD_ADDR           (CONFIG_SYS_SDRAM_BASE + SZ_2M)
> +
> +#define CONFIG_SYS_MALLOC_LEN          SZ_8M
> +
> +#define CONFIG_SYS_BOOTM_LEN           SZ_64M
> +
> +#define CONFIG_STANDALONE_LOAD_ADDR    0x80200000
> +
> +#define CONFIG_SYS_PCI_64BIT           1       /* enable 64-bit resources */
> +
> +#define CONFIG_SYS_CACHELINE_SIZE      64
> +
> +#define CONFIG_USB_OHCI_NEW
> +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     4
> +
> +/* Environment options */
> +
> +#ifndef CONFIG_SPL_BUILD
> +#define BOOT_TARGET_DEVICES(func) \
> +       func(NVME, nvme, 0) \
> +       func(USB, usb, 0) \
> +       func(MMC, mmc, 0) \
> +       func(PXE, pxe, na) \
> +       func(DHCP, dhcp, na)
> +
> +#include <config_distro_bootcmd.h>
> +
> +#define TYPE_GUID_LOADER1      "5B193300-FC78-40CD-8002-E86C45580B47"
> +#define TYPE_GUID_LOADER2      "2E54B353-1271-4842-806F-E436D6AF6985"
> +#define TYPE_GUID_SYSTEM       "0FC63DAF-8483-4772-8E79-3D69D8477DE4"
> +
> +#define PARTS_DEFAULT \
> +       "name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1};" \
> +       "name=loader2,size=4MB,type=${type_guid_gpt_loader2};" \
> +       "name=system,size=-,bootable,type=${type_guid_gpt_system};"
> +
> +#define CONFIG_EXTRA_ENV_SETTINGS \
> +       "fdt_high=0xffffffffffffffff\0" \
> +       "initrd_high=0xffffffffffffffff\0" \
> +       "kernel_addr_r=0x84000000\0" \
> +       "fdt_addr_r=0x88000000\0" \
> +       "scriptaddr=0x88100000\0" \
> +       "pxefile_addr_r=0x88200000\0" \
> +       "ramdisk_addr_r=0x88300000\0" \
> +       "kernel_comp_addr_r=0x90000000\0" \
> +       "kernel_comp_size=0x4000000\0" \
> +       "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \
> +       "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
> +       "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
> +       "partitions=" PARTS_DEFAULT "\0" \
> +       BOOTENV
> +
> +#define CONFIG_PREBOOT \
> +       "setenv fdt_addr ${fdtcontroladdr};" \
> +       "fdt addr ${fdtcontroladdr};"
> +#endif /* CONFIG_SPL_BUILD */
> +
> +#endif /* __SIFIVE_UNMATCHED_H */
> --
> 2.7.4
>

Regards,
Bin
Green Wan March 16, 2021, 2:33 a.m. UTC | #2 
On Thu, Mar 11, 2021 at 10:21 PM Bin Meng <bmeng.cn@gmail.com> wrote:

> On Thu, Mar 11, 2021 at 9:50 PM Green Wan <green.wan@sifive.com> wrote:
> >
> > Add dts, defconfig and board support for HiFive Unmatched.
> >
> > Signed-off-by: Green Wan <green.wan@sifive.com>
> > ---
> >  arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489
> ++++++++++++++++++++
> >  arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi    |   40 +
> >  arch/riscv/dts/hifive-unmatched-a00.dts            |  263 ++++
> >  board/sifive/fu540/Kconfig                         |    1 -
> >  board/sifive/fu540/fu540.c                         |    2 +-
>
> It looks these fu540 changes are not needed?
>
Let me remove the change for fu540 first and check on fu540.


>
> >  board/sifive/hifive_unmatched_fu740/Kconfig        |   50 +
> >  board/sifive/hifive_unmatched_fu740/MAINTAINERS    |    9 +
> >  board/sifive/hifive_unmatched_fu740/Makefile       |    9 +

>  .../hifive-unmatched-fu740.c                       |   24 +
> >  board/sifive/hifive_unmatched_fu740/spl.c          |   85 ++
> >  configs/sifive_hifive_unmatched_fu740_defconfig    |   57 +
>
  I'd like to rename  "board/sifive/hifive_unmatched_fu740" to the shorter
name "board/sifive/unmatched". And
"configs/sifive_hifive_unmatched_fu740_defconfig" to
"configs/sifive_unmatched_defconfig" in v2 patch.


> >  doc/board/sifive/fu540.rst                         |   19 +-
>
> here?
>
> >  doc/board/sifive/hifive_unmatched_fu740.rst        |  532 +++++++
> >  drivers/reset/Kconfig                              |    2 +-
> >  include/configs/sifive-fu540.h                     |    5 -
>
> and here?
>
> >  include/configs/sifive-hifive-unmatched-fu740.h    |   88 ++
> >  16 files changed, 2656 insertions(+), 19 deletions(-)
> >  create mode 100644 arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
> >  create mode 100644 arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
> >  create mode 100644 arch/riscv/dts/hifive-unmatched-a00.dts
> >  create mode 100644 board/sifive/hifive_unmatched_fu740/Kconfig
> >  create mode 100644 board/sifive/hifive_unmatched_fu740/MAINTAINERS
> >  create mode 100644 board/sifive/hifive_unmatched_fu740/Makefile
> >  create mode 100644
> board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c
> >  create mode 100644 board/sifive/hifive_unmatched_fu740/spl.c
> >  create mode 100644 configs/sifive_hifive_unmatched_fu740_defconfig
> >  create mode 100644 doc/board/sifive/hifive_unmatched_fu740.rst
> >  create mode 100644 include/configs/sifive-hifive-unmatched-fu740.h
> >
> > diff --git a/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
> b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
> > new file mode 100644
> > index 0000000..4209491
> > --- /dev/null
> > +++ b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
>
> [snip]
>
> > diff --git a/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
> b/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
> > new file mode 100644
> > index 0000000..3dcd2b4
> > --- /dev/null
> > +++ b/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
> > @@ -0,0 +1,40 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (C) 2020-2021 SiFive, Inc
> > + */
> > +
> > +#include "fu740-c000-u-boot.dtsi"
> > +#include "fu740-hifive-unmatched-a00-ddr.dtsi"
> > +
> > +/ {
> > +       aliases {
> > +               spi0 = &spi0;
> > +       };
> > +
> > +       memory@80000000 {
> > +               u-boot,dm-spl;
> > +       };
> > +
> > +       hfclk {
> > +               u-boot,dm-spl;
> > +       };
> > +
> > +       rtcclk {
> > +               u-boot,dm-spl;
> > +       };
> > +
> > +};
> > +
> > +&clint {
> > +       clocks = <&rtcclk>;
> > +};
> > +
> > +&spi0 {
> > +       mmc@0 {
> > +               u-boot,dm-spl;
> > +       };
> > +};
> > +
> > +&gpio {
> > +       u-boot,dm-spl;
> > +};
> > diff --git a/arch/riscv/dts/hifive-unmatched-a00.dts
> b/arch/riscv/dts/hifive-unmatched-a00.dts
> > new file mode 100644
> > index 0000000..92410b4
> > --- /dev/null
> > +++ b/arch/riscv/dts/hifive-unmatched-a00.dts
> > @@ -0,0 +1,263 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/* Copyright (c) 2019-2021 SiFive, Inc */
> > +
> > +#include "fu740-c000.dtsi"
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
> > +#define RTCCLK_FREQ            1000000
> > +
> > +/ {
> > +       #address-cells = <2>;
> > +       #size-cells = <2>;
> > +       model = "SiFive HiFive Unmatched A00";
> > +       compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
> > +                    "sifive,fu740";
> > +
> > +       chosen {
> > +               stdout-path = "serial0";
> > +       };
> > +
> > +       cpus {
> > +               timebase-frequency = <RTCCLK_FREQ>;
> > +       };
> > +
> > +       memory@80000000 {
> > +               device_type = "memory";
> > +               reg = <0x0 0x80000000 0x4 0x00000000>;
> > +       };
> > +
> > +       soc {
> > +       };
> > +
> > +       hfclk: hfclk {
> > +               #clock-cells = <0>;
> > +               compatible = "fixed-clock";
> > +               clock-frequency = <26000000>;
> > +               clock-output-names = "hfclk";
> > +       };
> > +
> > +       rtcclk: rtcclk {
> > +               #clock-cells = <0>;
> > +               compatible = "fixed-clock";
> > +               clock-frequency = <RTCCLK_FREQ>;
> > +               clock-output-names = "rtcclk";
> > +       };
> > +};
> > +
> > +&uart0 {
> > +       status = "okay";
> > +};
> > +
> > +&uart1 {
> > +       status = "okay";
> > +};
> > +
>
> > +
> > +&qspi0 {
> > +       status = "okay";
> > +       flash@0 {
> > +               compatible = "issi,is25wp256", "jedec,spi-nor";
> > +               reg = <0>;
> > +               spi-max-frequency = <50000000>;
> > +               m25p,fast-read;
> > +               spi-tx-bus-width = <4>;
> > +               spi-rx-bus-width = <4>;
> > +       };
> > +};
> > +
> > +&spi0 {
> > +       status = "okay";
> > +       mmc@0 {
> > +               compatible = "mmc-spi-slot";
> > +               reg = <0>;
> > +               spi-max-frequency = <20000000>;
> > +               voltage-ranges = <3300 3300>;
> > +               disable-wp;
> > +       };
> > +};
> > +
> > +&eth0 {
> > +       status = "okay";
> > +       phy-mode = "gmii";
> > +       phy-handle = <&phy0>;
> > +       phy0: ethernet-phy@0 {
> > +               reg = <0>;
> > +       };
> > +};
> > +
> > +&pwm0 {
> > +       status = "okay";
> > +};
> > +
> > +&pwm1 {
> > +       status = "okay";
> > +};
> > +
> > +&gpio {
> > +       status = "okay";
> > +};
> > diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
> > index 64fdbd4..e70d1e5 100644
> > --- a/board/sifive/fu540/Kconfig
> > +++ b/board/sifive/fu540/Kconfig
> > @@ -47,6 +47,5 @@ config BOARD_SPECIFIC_OPTIONS # dummy
> >         imply SPI_FLASH_ISSI
> >         imply SYSRESET
> >         imply SYSRESET_GPIO
> > -       imply CMD_I2C
> >
> >  endif
> > diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
> > index a4e7822..54e5a4c 100644
> > --- a/board/sifive/fu540/fu540.c
> > +++ b/board/sifive/fu540/fu540.c
> > @@ -58,7 +58,7 @@ static u32 fu540_read_serialnum(void)
> >
> >         /* init OTP */
> >         ret = uclass_get_device_by_driver(UCLASS_MISC,
> > -                                         DM_DRIVER_GET(sifive_otp),
> &dev);
> > +                                         DM_GET_DRIVER(sifive_otp),
> &dev);
> >
> >         if (ret) {
> >                 debug("%s: could not find otp device\n", __func__);
> > diff --git a/board/sifive/hifive_unmatched_fu740/Kconfig
> b/board/sifive/hifive_unmatched_fu740/Kconfig
> > new file mode 100644
> > index 0000000..53c87c6
> > --- /dev/null
> > +++ b/board/sifive/hifive_unmatched_fu740/Kconfig
> > @@ -0,0 +1,50 @@
> > +if TARGET_SIFIVE_UNMATCHED
> > +
> > +config SYS_BOARD
> > +       default "hifive_unmatched_fu740"
> > +
> > +config SYS_VENDOR
> > +       default "sifive"
> > +
> > +config SYS_CPU
> > +       default "fu740"
> > +
> > +config SYS_CONFIG_NAME
> > +       default "sifive-hifive-unmatched-fu740"
> > +
> > +config SYS_TEXT_BASE
> > +       default 0x80200000 if SPL
> > +       default 0x80000000 if !RISCV_SMODE
> > +       default 0x80200000 if RISCV_SMODE
> > +
> > +config SPL_TEXT_BASE
> > +       default 0x08000000
> > +
> > +config SPL_OPENSBI_LOAD_ADDR
> > +       default 0x80000000
> > +
> > +config BOARD_SPECIFIC_OPTIONS # dummy
> > +       def_bool y
> > +       select SIFIVE_FU740
> > +       select SUPPORT_SPL
> > +       select RESET_SIFIVE
> > +       imply CMD_DHCP
> > +       imply CMD_EXT2
> > +       imply CMD_EXT4
> > +       imply CMD_FAT
> > +       imply CMD_FS_GENERIC
> > +       imply CMD_GPT
> > +       imply PARTITION_TYPE_GUID
> > +       imply CMD_NET
> > +       imply CMD_PING
> > +       imply CMD_SF
> > +       imply DOS_PARTITION
> > +       imply EFI_PARTITION
> > +       imply IP_DYN
> > +       imply ISO_PARTITION
> > +       imply PHY_LIB
> > +       imply PHY_MSCC
> > +       imply SYSRESET
> > +       imply SYSRESET_GPIO
> > +
> > +endif
> > diff --git a/board/sifive/hifive_unmatched_fu740/MAINTAINERS
> b/board/sifive/hifive_unmatched_fu740/MAINTAINERS
> > new file mode 100644
> > index 0000000..783b20d
> > --- /dev/null
> > +++ b/board/sifive/hifive_unmatched_fu740/MAINTAINERS
> > @@ -0,0 +1,9 @@
> > +SiFive HiFive Unmatched FU740 BOARD
> > +M:     Paul Walmsley <paul.walmsley@sifive.com>
> > +M:     Pragnesh Patel <pragnesh.patel@sifive.com>
> > +M:     Green Wan <green.wan@sifive.com>
> > +S:     Maintained
> > +F:     board/sifive/hifive_unmatched_fu740/
> > +F:     doc/board/sifive/hifive-unmatched-fu740.rst
> > +F:     include/configs/sifive-hifive-unmatched-fu740.h
> > +F:     configs/sifive_hifive_unmatched_fu740_defconfig
> > diff --git a/board/sifive/hifive_unmatched_fu740/Makefile
> b/board/sifive/hifive_unmatched_fu740/Makefile
> > new file mode 100644
> > index 0000000..aeab025
> > --- /dev/null
> > +++ b/board/sifive/hifive_unmatched_fu740/Makefile
> > @@ -0,0 +1,9 @@
> > +# SPDX-License-Identifier: GPL-2.0+
> > +#
> > +# Copyright (c) 2020 SiFive, Inc
> > +
> > +obj-y   += hifive-unmatched-fu740.o
> > +
> > +ifdef CONFIG_SPL_BUILD
> > +obj-y += spl.o
> > +endif
> > diff --git
> a/board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c
> b/board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c
> > new file mode 100644
> > index 0000000..361bfbf
> > --- /dev/null
> > +++ b/board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c
> > @@ -0,0 +1,24 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (c) 2020, SiFive Inc
> > + *
> > + * Authors:
> > + *   Pragnesh Patel <pragnesh.patel@sifive.com>
> > + */
> > +
> > +#include <common.h>
> > +#include <dm.h>
> > +#include <asm/arch/cache.h>
> > +
> > +int board_init(void)
> > +{
> > +       int ret;
> > +
> > +       /* enable all cache ways */
> > +       ret = cache_enable_ways();
> > +       if (ret) {
> > +               debug("%s: could not enable cache ways\n", __func__);
> > +               return ret;
> > +       }
> > +       return 0;
> > +}
> > diff --git a/board/sifive/hifive_unmatched_fu740/spl.c
> b/board/sifive/hifive_unmatched_fu740/spl.c
> > new file mode 100644
> > index 0000000..d8ee934
> > --- /dev/null
> > +++ b/board/sifive/hifive_unmatched_fu740/spl.c
> > @@ -0,0 +1,85 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * Copyright (c) 2020 SiFive, Inc
> > + *
> > + * Authors:
> > + *   Pragnesh Patel <pragnesh.patel@sifive.com>
> > + */
> > +
> > +#include <init.h>
> > +#include <spl.h>
> > +#include <misc.h>
> > +#include <log.h>
> > +#include <linux/delay.h>
> > +#include <linux/io.h>
> > +#include <asm/gpio.h>
> > +#include <asm/arch/gpio.h>
> > +#include <asm/arch/spl.h>
> > +
> > +#define GEM_PHY_RESET  SIFIVE_GENERIC_GPIO_NR(0, 12)
> > +
> > +#define MODE_SELECT_REG                0x1000
> > +#define MODE_SELECT_SD         0xb
> > +#define MODE_SELECT_MASK       GENMASK(3, 0)
> > +
> > +int spl_board_init_f(void)
> > +{
> > +       int ret;
> > +
> > +       ret = spl_soc_init();
> > +       if (ret) {
> > +               debug("HiFive Unmatched FU740 SPL init failed: %d\n",
> ret);
> > +               return ret;
> > +       }
> > +
> > +       /*
> > +        * GEMGXL init VSC8541 PHY reset sequence;
> > +        * leave pull-down active for 2ms
> > +        */
> > +       udelay(2000);
> > +       ret = gpio_request(GEM_PHY_RESET, "gem_phy_reset");
> > +       if (ret) {
> > +               debug("gem_phy_reset gpio request failed: %d\n", ret);
> > +               return ret;
> > +       }
> > +
> > +       /* Set GPIO 12 (PHY NRESET) */
> > +       ret = gpio_direction_output(GEM_PHY_RESET, 1);
> > +       if (ret) {
> > +               debug("gem_phy_reset gpio direction set failed: %d\n",
> ret);
> > +               return ret;
> > +       }
> > +
> > +       udelay(1);
> > +
> > +       /* Reset PHY again to enter unmanaged mode */
> > +       gpio_set_value(GEM_PHY_RESET, 0);
> > +       udelay(1);
> > +       gpio_set_value(GEM_PHY_RESET, 1);
> > +       mdelay(15);
> > +
> > +       return 0;
> > +}
> > +
> > +u32 spl_boot_device(void)
> > +{
> > +       u32 mode_select = readl((void *)MODE_SELECT_REG);
> > +       u32 boot_device = mode_select & MODE_SELECT_MASK;
> > +
> > +       switch (boot_device) {
> > +       case MODE_SELECT_SD:
> > +               return BOOT_DEVICE_MMC1;
>
> No booting from SPI flash support?
>
> We don't boot from SPI flash right now. We want users to boot the whole
chain from SD card to avoid outdated FW on flash.



> > +       default:
> > +               debug("Unsupported boot device 0x%x but trying MMC1\n",
> > +                     boot_device);
> > +               return BOOT_DEVICE_MMC1;
> > +       }
> > +}
> > +
> > +#ifdef CONFIG_SPL_LOAD_FIT
> > +int board_fit_config_name_match(const char *name)
> > +{
> > +       /* boot using first FIT config */
> > +       return 0;
> > +}
> > +#endif
> > diff --git a/configs/sifive_hifive_unmatched_fu740_defconfig
> b/configs/sifive_hifive_unmatched_fu740_defconfig
> > new file mode 100644
> > index 0000000..5ec1ee6
> > --- /dev/null
> > +++ b/configs/sifive_hifive_unmatched_fu740_defconfig
> > @@ -0,0 +1,57 @@
> > +CONFIG_RISCV=y
> > +CONFIG_SPL_GPIO_SUPPORT=y
> > +CONFIG_SYS_MALLOC_F_LEN=0x3000
> > +CONFIG_NR_DRAM_BANKS=1
> > +CONFIG_SPL_DM_SPI=y
> > +CONFIG_SPL_MMC_SUPPORT=y
> > +CONFIG_SPL=y
> > +CONFIG_SPL_SPI_SUPPORT=y
> > +CONFIG_DEFAULT_DEVICE_TREE="hifive-unmatched-a00"
> > +CONFIG_TARGET_SIFIVE_UNMATCHED=y
> > +CONFIG_ARCH_RV64I=y
> > +CONFIG_RISCV_SMODE=y
> > +CONFIG_DISTRO_DEFAULTS=y
> > +CONFIG_FIT=y
> > +CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
> > +CONFIG_DISPLAY_CPUINFO=y
> > +CONFIG_DISPLAY_BOARDINFO=y
> > +CONFIG_DISPLAY_BOARDINFO_LATE=y
> > +CONFIG_SPL_SEPARATE_BSS=y
> > +CONFIG_SPL_DM_RESET=y
> > +CONFIG_SPL_YMODEM_SUPPORT=y
> > +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> > +CONFIG_SPL_CLK=y
> > +CONFIG_DM_RESET=y
> > +CONFIG_CMD_PCI=y
> > +CONFIG_PCI=y
> > +CONFIG_DM_PCI=y
> > +CONFIG_PCI_PNP=y
> > +CONFIG_PCIE_SIFIVE_FU740=y
> > +CONFIG_NVME=y
> > +CONFIG_DM_ETH=y
> > +CONFIG_NETDEVICES=y
> > +CONFIG_E1000=y
> > +CONFIG_USB=y
> > +CONFIG_CMD_USB=y
> > +CONFIG_DM_USB=y
> > +CONFIG_USB_STORAGE=y
> > +CONFIG_USB_XHCI_HCD=y
> > +CONFIG_USB_XHCI_PCI=y
> > +CONFIG_USB_EHCI_HCD=y
> > +CONFIG_USB_EHCI_GENERIC=y
> > +CONFIG_USB_OHCI_HCD=y
> > +CONFIG_USB_OHCI_GENERIC=y
> > +CONFIG_CMD_PART=y
> > +CONFIG_CMD_NVME=y
> > +CONFIG_SYS_USB_EVENT_POLL=y
> > +CONFIG_CMD_GPT=y
> > +CONFIG_CMD_GPT_RENAME=y
> > +CONFIG_CMD_EEPROM=y
> > +CONFIG_CMD_MEMINFO=y
> > +CONFIG_CMD_I2C=y
> > +CONFIG_DM_I2C=y
> > +CONFIG_SYS_I2C_OCORES=y
> > +CONFIG_CLK_SIFIVE_PRCI=y
> > +ONFIG_DM_PWM=y
> > +CONFIG_PWM_SIFIVE=y
> > +CONFIG_CMD_PWM=y
> > diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst
> > index 4e4c852..1ce9ab1 100644
> > --- a/doc/board/sifive/fu540.rst
> > +++ b/doc/board/sifive/fu540.rst
> > @@ -12,7 +12,6 @@ of running Linux.
> >
> >  Mainline support
> >  ----------------
> > -
> >  The support for following drivers are already enabled:
> >
> >  1. SiFive UART Driver.
> > @@ -25,7 +24,7 @@ Booting from MMC using FSBL
> >  ---------------------------
> >
> >  Building
> > -~~~~~~~~
> > +--------
> >
> >  1. Add the RISC-V toolchain to your PATH.
> >  2. Setup ARCH & cross compilation environment variable:
> > @@ -38,7 +37,7 @@ Building
> >  4. make
> >
> >  Flashing
> > -~~~~~~~~
> > +--------
> >
> >  The current U-Boot port is supported in S-mode only and loaded from
> DRAM.
> >
> > @@ -64,12 +63,11 @@ copied to the first partition of the sdcard.
> >      sudo dd if=<prior_stage_firmware_binary> of=/dev/disk2s1 bs=1024
> >
> >  Booting
> > -~~~~~~~
> > -
> > +-------
> >  Once you plugin the sdcard and power up, you should see the U-Boot
> prompt.
> >
> >  Sample boot log from HiFive Unleashed board
> > -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > +-------------------------------------------
> >
> >  .. code-block:: none
> >
> > @@ -419,7 +417,7 @@ Booting from MMC using U-Boot SPL
> >  ---------------------------------
> >
> >  Building
> > -~~~~~~~~
> > +--------
> >
> >  Before building U-Boot SPL, OpenSBI must be built first. OpenSBI can be
> >  cloned and built for FU540 as below:
> > @@ -443,7 +441,7 @@ This will generate spl/u-boot-spl.bin and FIT image
> (u-boot.itb)
> >
> >
> >  Flashing
> > -~~~~~~~~
> > +--------
> >
> >  ZSBL loads the U-Boot SPL (u-boot-spl.bin) from a partition with GUID
> type
> >  5B193300-FC78-40CD-8002-E86C45580B47
> > @@ -473,12 +471,11 @@ Program the SD card
> >         sudo dd if=u-boot.itb of=/dev/sda seek=2082
> >
> >  Booting
> > -~~~~~~~
> > -
> > +-------
> >  Once you plugin the sdcard and power up, you should see the U-Boot
> prompt.
> >
> >  Sample boot log from HiFive Unleashed board
> > -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> > +-------------------------------------------
> >
> >  .. code-block:: none
> >
> > diff --git a/doc/board/sifive/hifive_unmatched_fu740.rst
> b/doc/board/sifive/hifive_unmatched_fu740.rst
> > new file mode 100644
> > index 0000000..6670df5
> > --- /dev/null
> > +++ b/doc/board/sifive/hifive_unmatched_fu740.rst
> > @@ -0,0 +1,532 @@
> > +.. SPDX-License-Identifier: GPL-2.0+
> > +
> > +HiFive Unmatched
> > +================
> > +
> > +FU740-C000 RISC-V SoC
> > +---------------------
> > +The FU740-C000 is a 4+1 64-bit RISC-V core SoC from SiFive.
> > +
> > +The HiFive Unmatched development platform is based on FU740-C000 and
> capable
> > +of running Linux.
> > +
> > +Mainline support
> > +----------------
> > +The support for following drivers are already enabled:
> > +
> > +1. SiFive UART Driver.
> > +2. SiFive PRCI Driver for clock.
> > +3. Cadence MACB ethernet driver for networking support.
> > +4. SiFive SPI Driver.
> > +5. MMC SPI Driver for MMC/SD support.
> > +
> > +Booting from MMC using u-boot-spl
> > +---------------------------
> > +
> > +Building
> > +--------
> > +
> > +1. Add the RISC-V toolchain to your PATH.
> > +2. Setup ARCH & cross compilation environment variable:
> > +
> > +.. code-block:: none
> > +
> > +   export CROSS_COMPILE=<riscv64 toolchain prefix>
> > +
> > +3. make sifive_hifive_unmatched_fu740_defconfig
> > +4. make
> > +
> > +Flashing
> > +--------
> > +
> > +The current U-Boot port is supported in S-mode only and loaded from
> DRAM.
> > +
> > +A prior stage M-mode firmware/bootloader (e.g OpenSBI) is required to
> > +boot the u-boot.bin in S-mode and provide M-mode runtime services.
> > +
> > +Currently, the u-boot.bin is used as a payload of the OpenSBI FW_PAYLOAD
> > +firmware. We need to compile OpenSBI with below command:
> > +
> > +.. code-block:: none
> > +
> > +       make PLATFORM=generic FW_PAYLOAD_PATH=<path to u-boot-dtb.bin>
> > +
> > +More detailed description of steps required to build FW_PAYLOAD firmware
> > +is beyond the scope of this document. Please refer OpenSBI documenation.
> > +(Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git)
> > +
> > +Once the prior stage firmware/bootloader binary is generated, it should
> be
> > +copied to the first partition of the sdcard.
> > +
> > +.. code-block:: none
> > +
> > +    sudo dd if=<prior_stage_firmware_binary> of=/dev/disk2s1 bs=1024
> > +
> > +Booting
> > +-------
> > +Once you plugin the sdcard and power up, you should see the U-Boot
> prompt.
> > +
> > +Sample boot log from HiFive Unmatched board
> > +-------------------------------------------
> > +
> > +.. code-block:: none
> > +
> > +   U-Boot 2019.07-00024-g350ff02f5b (Jul 22 2019 - 11:45:02 +0530)
>
> This seems to be pretty old U-Boot
>
> will fix outdated content.

> > +
> > +   CPU:   rv64imafdc
> > +   Model: SiFive HiFive Unmatched A00
> > +   DRAM:  8 GiB
> > +   MMC:   spi@10050000:mmc@0: 0
> > +   In:    serial@10010000
> > +   Out:   serial@10010000
> > +   Err:   serial@10010000
> > +   Net:   eth0: ethernet@10090000
> > +   Hit any key to stop autoboot:  0
> > +   => version
> > +   U-Boot 2019.07-00024-g350ff02f5b (Jul 22 2019 - 11:45:02 +0530)
> > +
> > +   riscv64-linux-gcc.br_real (Buildroot 2018.11-rc2-00003-ga0787e9)
> 8.2.0
> > +   GNU ld (GNU Binutils) 2.31.1
> > +   => mmc info
> > +   Device: spi@10050000:mmc@0
> > +   Manufacturer ID: 3
> > +   OEM: 5344
> > +   Name: SU08G
> > +   Bus Speed: 20000000
> > +   Mode: SD Legacy
> > +   Rd Block Len: 512
> > +   SD version 2.0
> > +   High Capacity: Yes
> > +   Capacity: 7.4 GiB
> > +   Bus Width: 1-bit
> > +   Erase Group Size: 512 Bytes
> > +   => mmc part
> > +
> > +   Partition Map for MMC device 0  --   Partition Type: EFI
> > +
> > +   Part    Start LBA       End LBA         Name
> > +           Attributes
> > +           Type GUID
> > +           Partition GUID
> > +     1     0x00000800      0x000107ff      "bootloader"
> > +           attrs:  0x0000000000000000
> > +           type:   2e54b353-1271-4842-806f-e436d6af6985
> > +           guid:   393bbd36-7111-491c-9869-ce24008f6403
> > +     2     0x00040800      0x00ecdfde      ""
> > +           attrs:  0x0000000000000000
> > +           type:   0fc63daf-8483-4772-8e79-3d69d8477de4
> > +           guid:   7fc9a949-5480-48c7-b623-04923080757f
> > +
> > +Now you can configure your networking, tftp server and use tftp boot
> method to
> > +load uImage.
> > +
> > +.. code-block:: none
> > +
> > +   => setenv ipaddr 10.206.7.133
> > +   => setenv netmask 255.255.252.0
> > +   => setenv serverip 10.206.4.143
> > +   => setenv gateway 10.206.4.1
> > +
> > +If you want to use a flat kernel image such as Image file
> > +
> > +.. code-block:: none
> > +
> > +   => tftpboot ${kernel_addr_r} /sifive/fu740/Image
> > +   ethernet@10090000: PHY present at 0
> > +   ethernet@10090000: Starting autonegotiation...
> > +   ethernet@10090000: Autonegotiation complete
> > +   ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3c00)
> > +   Using ethernet@10090000 device
> > +   TFTP from server 10.206.4.143; our IP address is 10.206.7.133
> > +   Filename '/sifive/fu740/Image'.
> > +   Load address: 0x84000000
> > +   Loading:
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +            ##########################################
> > +            1.2 MiB/s
> > +   done
> > +   Bytes transferred = 8867100 (874d1c hex)
> > +
> > +Or if you want to use a compressed kernel image file such as Image.gz
> > +
> > +.. code-block:: none
> > +
> > +   => tftpboot ${kernel_addr_r} /sifive/fu740/Image.gz
> > +   ethernet@10090000: PHY present at 0
> > +   ethernet@10090000: Starting autonegotiation...
> > +   ethernet@10090000: Autonegotiation complete
> > +   ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3c00)
> > +   Using ethernet@10090000 device
> > +   TFTP from server 10.206.4.143; our IP address is 10.206.7.133
> > +   Filename '/sifive/fu740/Image.gz'.
> > +   Load address: 0x84000000
> > +   Loading:
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +            ##########################################
> > +            1.2 MiB/s
> > +   done
> > +   Bytes transferred = 4809458 (4962f2 hex)
> > +   =>setenv kernel_comp_addr_r 0x90000000
> > +   =>setenv kernel_comp_size 0x500000
> > +
> > +By this time, correct kernel image is loaded and required environment
> variables
> > +are set. You can proceed to load the ramdisk and device tree from the
> tftp server
> > +as well.
> > +
> > +.. code-block:: none
> > +
> > +   => tftpboot ${ramdisk_addr_r} /sifive/fu740/uRamdisk
> > +   ethernet@10090000: PHY present at 0
> > +   ethernet@10090000: Starting autonegotiation...
> > +   ethernet@10090000: Autonegotiation complete
> > +   ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3c00)
> > +   Using ethernet@10090000 device
> > +   TFTP from server 10.206.4.143; our IP address is 10.206.7.133
> > +   Filename '/sifive/fu740/uRamdisk'.
> > +   Load address: 0x88300000
> > +   Loading:
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +
> #################################################################
> > +            ##############
> > +            418.9 KiB/s
> > +   done
> > +   Bytes transferred = 2398272 (249840 hex)
> > +   => tftpboot ${fdt_addr_r} /sifive/fu740/hifive-unmatched-a00.dtb
> > +   ethernet@10090000: PHY present at 0
> > +   ethernet@10090000: Starting autonegotiation...
> > +   ethernet@10090000: Autonegotiation complete
> > +   ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x7c00)
> > +   Using ethernet@10090000 device
> > +   TFTP from server 10.206.4.143; our IP address is 10.206.7.133
> > +   Filename '/sifive/fu740/hifive-unmatched-a00.dtb'.
> > +   Load address: 0x88000000
> > +   Loading: ##
> > +            1000 Bytes/s
> > +   done
> > +   Bytes transferred = 5614 (15ee hex)
> > +   => setenv bootargs "root=/dev/ram rw console=ttySIF0 ip=dhcp
> earlycon=sbi"
> > +   => booti ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}
> > +   ## Loading init Ramdisk from Legacy Image at 88300000 ...
> > +      Image Name:   Linux RootFS
> > +      Image Type:   RISC-V Linux RAMDisk Image (uncompressed)
> > +      Data Size:    2398208 Bytes = 2.3 MiB
> > +      Load Address: 00000000
> > +      Entry Point:  00000000
> > +      Verifying Checksum ... OK
> > +   ## Flattened Device Tree blob at 88000000
> > +      Booting using the fdt blob at 0x88000000
> > +      Using Device Tree in place at 0000000088000000, end
> 00000000880045ed
> > +
> > +   Starting kernel ...
> > +
> > +   [    0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000
> > +   [    0.000000] Linux version 5.3.0-rc1-00003-g460ac558152f
> (anup@anup-lab-machine) (gcc version 8.2.0 (Buildroot
> 2018.11-rc2-00003-ga0787e9)) #6 SMP Mon Jul 22 10:01:01 IST 2019
>
> Looks this is an old kernel used for testing? I doubt it contains the
> new fu740-prci driver and PCIe support.
>
> > +   [    0.000000] earlycon: sbi0 at I/O port 0x0 (options '')
> > +   [    0.000000] printk: bootconsole [sbi0] enabled
> > +   [    0.000000] Initial ramdisk at: 0x(____ptrval____) (2398208 bytes)
> > +   [    0.000000] Zone ranges:
> > +   [    0.000000]   DMA32    [mem 0x0000000080200000-0x00000000ffffffff]
> > +   [    0.000000]   Normal   [mem 0x0000000100000000-0x000000027fffffff]
> > +   [    0.000000] Movable zone start for each node
> > +   [    0.000000] Early memory node ranges
> > +   [    0.000000]   node   0: [mem
> 0x0000000080200000-0x000000027fffffff]
> > +   [    0.000000] Initmem setup node 0 [mem
> 0x0000000080200000-0x000000027fffffff]
> > +   [    0.000000] software IO TLB: mapped [mem 0xfbfff000-0xfffff000]
> (64MB)
> > +   [    0.000000] CPU with hartid=0 is not available
> > +   [    0.000000] CPU with hartid=0 is not available
> > +   [    0.000000] elf_hwcap is 0x112d
> > +   [    0.000000] percpu: Embedded 18 pages/cpu s34584 r8192 d30952
> u73728
> > +   [    0.000000] Built 1 zonelists, mobility grouping on.  Total
> pages: 2067975
> > +   [    0.000000] Kernel command line: root=/dev/ram rw console=ttySIF0
> ip=dhcp earlycon=sbi
> > +   [    0.000000] Dentry cache hash table entries: 1048576 (order: 11,
> 8388608 bytes, linear)
> > +   [    0.000000] Inode-cache hash table entries: 524288 (order: 10,
> 4194304 bytes, linear)
> > +   [    0.000000] Sorting __ex_table...
> > +   [    0.000000] mem auto-init: stack:off, heap alloc:off, heap
> free:off
> > +   [    0.000000] Memory: 8182308K/8386560K available (5916K kernel
> code, 368K rwdata, 1840K rodata, 213K init, 304K bss, 204252K reserved, 0K
> cma-reserved)
> > +   [    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4,
> Nodes=1
> > +   [    0.000000] rcu: Hierarchical RCU implementation.
> > +   [    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=8 to
> nr_cpu_ids=4.
> > +   [    0.000000] rcu: RCU calculated value of scheduler-enlistment
> delay is 25 jiffies.
> > +   [    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16,
> nr_cpu_ids=4
> > +   [    0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
> > +   [    0.000000] plic: mapped 53 interrupts with 4 handlers for 9
> contexts.
> > +   [    0.000000] riscv_timer_init_dt: Registering clocksource cpuid
> [0] hartid [1]
> > +   [    0.000000] clocksource: riscv_clocksource: mask:
> 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns
> > +   [    0.000006] sched_clock: 64 bits at 1000kHz, resolution 1000ns,
> wraps every 2199023255500ns
> > +   [    0.008559] Console: colour dummy device 80x25
> > +   [    0.012989] Calibrating delay loop (skipped), value calculated
> using timer frequency.. 2.00 BogoMIPS (lpj=4000)
> > +   [    0.023104] pid_max: default: 32768 minimum: 301
> > +   [    0.028273] Mount-cache hash table entries: 16384 (order: 5,
> 131072 bytes, linear)
> > +   [    0.035765] Mountpoint-cache hash table entries: 16384 (order: 5,
> 131072 bytes, linear)
> > +   [    0.045307] rcu: Hierarchical SRCU implementation.
> > +   [    0.049875] smp: Bringing up secondary CPUs ...
> > +   [    0.055729] smp: Brought up 1 node, 4 CPUs
> > +   [    0.060599] devtmpfs: initialized
> > +   [    0.064819] random: get_random_u32 called from
> bucket_table_alloc.isra.10+0x4e/0x160 with crng_init=0
> > +   [    0.073720] clocksource: jiffies: mask: 0xffffffff max_cycles:
> 0xffffffff, max_idle_ns: 7645041785100000 ns
> > +   [    0.083176] futex hash table entries: 1024 (order: 4, 65536
> bytes, linear)
> > +   [    0.090721] NET: Registered protocol family 16
> > +   [    0.106319] vgaarb: loaded
> > +   [    0.108670] SCSI subsystem initialized
> > +   [    0.112515] usbcore: registered new interface driver usbfs
> > +   [    0.117758] usbcore: registered new interface driver hub
> > +   [    0.123167] usbcore: registered new device driver usb
> > +   [    0.128905] clocksource: Switched to clocksource riscv_clocksource
> > +   [    0.141239] NET: Registered protocol family 2
> > +   [    0.145506] tcp_listen_portaddr_hash hash table entries: 4096
> (order: 4, 65536 bytes, linear)
> > +   [    0.153754] TCP established hash table entries: 65536 (order: 7,
> 524288 bytes, linear)
> > +   [    0.163466] TCP bind hash table entries: 65536 (order: 8, 1048576
> bytes, linear)
> > +   [    0.173468] TCP: Hash tables configured (established 65536 bind
> 65536)
> > +   [    0.179739] UDP hash table entries: 4096 (order: 5, 131072 bytes,
> linear)
> > +   [    0.186627] UDP-Lite hash table entries: 4096 (order: 5, 131072
> bytes, linear)
> > +   [    0.194117] NET: Registered protocol family 1
> > +   [    0.198417] RPC: Registered named UNIX socket transport module.
> > +   [    0.203887] RPC: Registered udp transport module.
> > +   [    0.208664] RPC: Registered tcp transport module.
> > +   [    0.213429] RPC: Registered tcp NFSv4.1 backchannel transport
> module.
> > +   [    0.219944] PCI: CLS 0 bytes, default 64
> > +   [    0.224170] Unpacking initramfs...
> > +   [    0.262347] Freeing initrd memory: 2336K
> > +   [    0.266531] workingset: timestamp_bits=62 max_order=21
> bucket_order=0
> > +   [    0.280406] NFS: Registering the id_resolver key type
> > +   [    0.284798] Key type id_resolver registered
> > +   [    0.289048] Key type id_legacy registered
> > +   [    0.293114] nfs4filelayout_init: NFSv4 File Layout Driver
> Registering...
> > +   [    0.300262] NET: Registered protocol family 38
> > +   [    0.304432] Block layer SCSI generic (bsg) driver version 0.4
> loaded (major 254)
> > +   [    0.311862] io scheduler mq-deadline registered
> > +   [    0.316461] io scheduler kyber registered
> > +   [    0.356421] Serial: 8250/16550 driver, 4 ports, IRQ sharing
> disabled
> > +   [    0.363004] 10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 4,
> base_baud = 0) is a SiFive UART v0
> > +   [    0.371468] printk: console [ttySIF0] enabled
> > +   [    0.371468] printk: console [ttySIF0] enabled
> > +   [    0.380223] printk: bootconsole [sbi0] disabled
> > +   [    0.380223] printk: bootconsole [sbi0] disabled
> > +   [    0.389589] 10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 1,
> base_baud = 0) is a SiFive UART v0
> > +   [    0.398680] [drm] radeon kernel modesetting enabled.
> > +   [    0.412395] loop: module loaded
> > +   [    0.415214] sifive_spi 10040000.spi: mapped; irq=3, cs=1
> > +   [    0.420628] sifive_spi 10050000.spi: mapped; irq=5, cs=1
> > +   [    0.425897] libphy: Fixed MDIO Bus: probed
> > +   [    0.429964] macb 10090000.ethernet: Registered clk switch
> 'sifive-gemgxl-mgmt'
> > +   [    0.436743] macb: GEM doesn't support hardware ptp.
> > +   [    0.441621] libphy: MACB_mii_bus: probed
> > +   [    0.601316] Microsemi VSC8541 SyncE
> 10090000.ethernet-ffffffff:00: attached PHY driver [Microsemi VSC8541
> SyncE] (mii_bus:phy_addr=10090000.ethernet-ffffffff:00, irq=POLL)
> > +   [    0.615857] macb 10090000.ethernet eth0: Cadence GEM rev
> 0x10070109 at 0x10090000 irq 6 (70:b3:d5:92:f2:f3)
> > +   [    0.625634] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
> > +   [    0.631381] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
> > +   [    0.637382] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI)
> Driver
> > +   [    0.643799] ehci-pci: EHCI PCI platform driver
> > +   [    0.648261] ehci-platform: EHCI generic platform driver
> > +   [    0.653497] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
> > +   [    0.659599] ohci-pci: OHCI PCI platform driver
> > +   [    0.664055] ohci-platform: OHCI generic platform driver
> > +   [    0.669448] usbcore: registered new interface driver uas
> > +   [    0.674575] usbcore: registered new interface driver usb-storage
> > +   [    0.680642] mousedev: PS/2 mouse device common for all mice
> > +   [    0.709493] mmc_spi spi1.0: SD/MMC host mmc0, no DMA, no WP, no
> poweroff, cd polling
> > +   [    0.716615] usbcore: registered new interface driver usbhid
> > +   [    0.722023] usbhid: USB HID core driver
> > +   [    0.726738] NET: Registered protocol family 10
> > +   [    0.731359] Segment Routing with IPv6
> > +   [    0.734332] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
> > +   [    0.740687] NET: Registered protocol family 17
> > +   [    0.744660] Key type dns_resolver registered
> > +   [    0.806775] mmc0: host does not support reading read-only switch,
> assuming write-enable
> > +   [    0.814020] mmc0: new SDHC card on SPI
> > +   [    0.820137] mmcblk0: mmc0:0000 SU08G 7.40 GiB
> > +   [    0.850220]  mmcblk0: p1 p2
> > +   [    3.821524] macb 10090000.ethernet eth0: link up (1000/Full)
> > +   [    3.828938] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes
> ready
> > +   [    3.848919] Sending DHCP requests .., OK
> > +   [    6.252076] IP-Config: Got DHCP answer from 10.206.4.1, my
> address is 10.206.7.133
> > +   [    6.259624] IP-Config: Complete:
> > +   [    6.262831]      device=eth0, hwaddr=70:b3:d5:92:f2:f3,
> ipaddr=10.206.7.133, mask=255.255.252.0, gw=10.206.4.1
> > +   [    6.272809]      host=dhcp-10-206-7-133, domain=
> sdcorp.global.sandisk.com, nis-domain=(none)
> > +   [    6.281228]      bootserver=10.206.126.11,
> rootserver=10.206.126.11, rootpath=
> > +   [    6.281232]      nameserver0=10.86.1.1, nameserver1=10.86.2.1
> > +   [    6.294179]      ntpserver0=10.86.1.1, ntpserver1=10.86.2.1
> > +   [    6.301026] Freeing unused kernel memory: 212K
> > +   [    6.304683] This architecture does not have kernel memory
> protection.
> > +   [    6.311121] Run /init as init process
> > +              _  _
> > +             | ||_|
> > +             | | _ ____  _   _  _  _
> > +             | || |  _ \| | | |\ \/ /
> > +             | || | | | | |_| |/    \
> > +             |_||_|_| |_|\____|\_/\_/
> > +
> > +                  Busybox Rootfs
> > +
> > +   Please press Enter to activate this console.
> > +   / #
> > +
> > +Booting from MMC using U-Boot SPL
> > +---------------------------------
> > +
> > +Building
> > +--------
> > +
> > +Before building U-Boot SPL, OpenSBI must be built first. OpenSBI can be
> > +cloned and built for FU740 as below:
> > +
> > +.. code-block:: console
> > +
> > +       git clone https://github.com/riscv/opensbi.git
> > +       cd opensbi
> > +       make PLATFORM=generic
> > +       export OPENSBI=<path to
> opensbi/build/platform/generic/firmware/fw_dynamic.bin>
> > +
> > +Now build the U-Boot SPL and U-Boot proper
> > +
> > +.. code-block:: console
> > +
> > +       cd <U-Boot-dir>
> > +       make sifive_hifive_unmatched_fu740_defconfig
> > +       make
> > +
> > +This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
> > +
> > +
> > +Flashing
> > +--------
> > +
> > +ZSBL loads the U-Boot SPL (u-boot-spl.bin) from a partition with GUID
> type
> > +5B193300-FC78-40CD-8002-E86C45580B47
> > +
> > +U-Boot SPL expects a U-Boot FIT image (u-boot.itb) from a partition
> with GUID
> > +type 2E54B353-1271-4842-806F-E436D6AF6985
> > +
> > +FIT image (u-boot.itb) is a combination of fw_dynamic.bin,
> u-boot-nodtb.bin and
> > +device tree blob (hifive-unmatched-a00.dtb)
> > +
> > +Format the SD card (make sure the disk has GPT, otherwise use gdisk to
> switch)
> > +
> > +.. code-block:: none
> > +
> > +       # sudo sgdisk --clear \
> > +       > --set-alignment=2 \
> > +       > --new=1:34:2081 --change-name=1:loader1
> --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \
> > +       > --new=2:2082:10273 --change-name=2:loader2
> --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \
> > +       > --new=3:10274: --change-name=3:rootfs
> --typecode=3:0FC63DAF-8483-4772-8E79-3D69D8477DE4 \
> > +       > /dev/sda
> > +
> > +Program the SD card
> > +
> > +.. code-block:: none
> > +
> > +       sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34
> > +       sudo dd if=u-boot.itb of=/dev/sda seek=2082
> > +
> > +Booting
> > +-------
> > +Once you plugin the sdcard and power up, you should see the U-Boot
> prompt.
> > +
> > +Sample boot log from HiFive Unmatched board
> > +-------------------------------------------
> > +
> > +.. code-block:: none
> > +
> > +        U-Boot SPL 2021.04-rc3 (Mar 11 2021 - 08:07:46 +0000)
> > +        Trying to boot from MMC1
> > +
> > +
> > +        U-Boot 2021.04-rc3 (Mar 11 2021 - 08:07:46 +0000)
> > +
> > +        CPU:   rv64imafdc
> > +        Model: SiFive HiFive Unmatched A00
> > +        DRAM:  16 GiB
> > +        MMC:   spi@10050000:mmc@0: 0
> > +        In:    serial@10010000
> > +        Out:   serial@10010000
> > +        Err:   serial@10010000
> > +        Model: SiFive HiFive Unmatched A00
> > +        Net:
> > +        Error: ethernet@10090000 address not set.
> > +        No ethernet found.
> > +
> > +        Hit any key to stop autoboot:  0
> > +        => version
> > +        U-Boot 2021.04-rc3 (Mar 11 2021 - 08:07:46 +0000)
> > +
> > +        riscv64-oe-linux-gcc (GCC) 10.2.0
> > +        GNU ld (GNU Binutils) 2.35.0.20200730
> > +        => mmc part
> > +
> > +        Partition Map for MMC device 0  --   Partition Type: EFI
> > +
> > +        Part    Start LBA       End LBA         Name
> > +        Attributes
> > +        Type GUID
> > +        Partition GUID
> > +        1     0x00000022      0x00000821      "primary"
> > +              attrs:  0x0000000000000000
> > +              type:   5b193300-fc78-40cd-8002-e86c45580b47
> > +              guid:   f4b7c671-63ec-4f3b-8f26-3f10407df3c7
> > +        2     0x00000822      0x00002821      "primary"
> > +              attrs:  0x0000000000000000
> > +              type:   2e54b353-1271-4842-806f-e436d6af6985
> > +              guid:   e48d9a09-ff68-4219-abb4-62917290de3c
> > +        3     0x00004000      0x00044fff      "boot"
> > +              attrs:  0x0000000000000004
> > +              type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
> > +              type:   data
> > +              guid:   6af708a6-0e40-4476-a900-cd59954034f1
> > +        4     0x00046000      0x03b723de      "root"
> > +              attrs:  0x0000000000000000
> > +              type:   0fc63daf-8483-4772-8e79-3d69d8477de4
> > +              type:   linux
> > +              guid:   038165a5-b704-4d96-9bc4-2533803c6620
> > +
> > diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
> > index f5b3f88..33bbbd5 100644
> > --- a/drivers/reset/Kconfig
> > +++ b/drivers/reset/Kconfig
> > @@ -166,7 +166,7 @@ config RESET_IPQ419
> >
> >  config RESET_SIFIVE
> >         bool "Reset Driver for SiFive SoC's"
> > -       depends on DM_RESET && CLK_SIFIVE_FU540_PRCI &&
> TARGET_SIFIVE_FU540
> > +       depends on DM_RESET && CLK_SIFIVE_PRCI && (TARGET_SIFIVE_FU540
> || TARGET_SIFIVE_HIFIVE_UNMATCHED_FU740)
> >         default y
> >         help
> >           PRCI module within SiFive SoC's provides mechanism to reset
> > diff --git a/include/configs/sifive-fu540.h
> b/include/configs/sifive-fu540.h
> > index 0d69d1c..c1c79db 100644
> > --- a/include/configs/sifive-fu540.h
> > +++ b/include/configs/sifive-fu540.h
> > @@ -36,11 +36,6 @@
> >
> >  #define CONFIG_STANDALONE_LOAD_ADDR    0x80200000
> >
> > -#define RISCV_MMODE_TIMERBASE          0x2000000
> > -#define RISCV_MMODE_TIMER_FREQ         1000000
> > -
> > -#define RISCV_SMODE_TIMER_FREQ         1000000
> > -
>
> These changes seem not needed?
>
> >  /* Environment options */
> >
> >  #ifndef CONFIG_SPL_BUILD
> > diff --git a/include/configs/sifive-hifive-unmatched-fu740.h
> b/include/configs/sifive-hifive-unmatched-fu740.h
> > new file mode 100644
> > index 0000000..b59df9c
> > --- /dev/null
> > +++ b/include/configs/sifive-hifive-unmatched-fu740.h
> > @@ -0,0 +1,88 @@
> > +/* SPDX-License-Identifier: GPL-2.0+ */
> > +/*
> > + * Copyright (c) 2020 SiFive, Inc
> > + *
> > + * Authors:
> > + *   Pragnesh Patel <pragnesh.patel@sifive.com>
> > + */
> > +
> > +#ifndef __SIFIVE_UNMATCHED_H
> > +#define __SIFIVE_UNMATCHED_H
> > +
> > +#include <linux/sizes.h>
> > +
> > +#ifdef CONFIG_SPL
> > +
> > +#define CONFIG_SPL_MAX_SIZE            0x00100000
> > +#define CONFIG_SPL_BSS_START_ADDR      0x85000000
> > +#define CONFIG_SPL_BSS_MAX_SIZE                0x00100000
> > +#define CONFIG_SYS_SPL_MALLOC_START    (CONFIG_SPL_BSS_START_ADDR + \
> > +                                        CONFIG_SPL_BSS_MAX_SIZE)
> > +#define CONFIG_SYS_SPL_MALLOC_SIZE     0x00100000
> > +
> > +#define CONFIG_SPL_STACK       (0x08000000 + 0x001D0000 - \
> > +                                GENERATED_GBL_DATA_SIZE)
> > +
> > +#endif
> > +
> > +#define CONFIG_SYS_SDRAM_BASE          0x80000000
> > +#define CONFIG_SYS_INIT_SP_ADDR                (CONFIG_SYS_SDRAM_BASE +
> SZ_2M)
> > +
> > +#define CONFIG_SYS_LOAD_ADDR           (CONFIG_SYS_SDRAM_BASE + SZ_2M)
> > +
> > +#define CONFIG_SYS_MALLOC_LEN          SZ_8M
> > +
> > +#define CONFIG_SYS_BOOTM_LEN           SZ_64M
> > +
> > +#define CONFIG_STANDALONE_LOAD_ADDR    0x80200000
> > +
> > +#define CONFIG_SYS_PCI_64BIT           1       /* enable 64-bit
> resources */
> > +
> > +#define CONFIG_SYS_CACHELINE_SIZE      64
> > +
> > +#define CONFIG_USB_OHCI_NEW
> > +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     4
> > +
> > +/* Environment options */
> > +
> > +#ifndef CONFIG_SPL_BUILD
> > +#define BOOT_TARGET_DEVICES(func) \
> > +       func(NVME, nvme, 0) \
> > +       func(USB, usb, 0) \
> > +       func(MMC, mmc, 0) \
> > +       func(PXE, pxe, na) \
> > +       func(DHCP, dhcp, na)
> > +
> > +#include <config_distro_bootcmd.h>
> > +
> > +#define TYPE_GUID_LOADER1      "5B193300-FC78-40CD-8002-E86C45580B47"
> > +#define TYPE_GUID_LOADER2      "2E54B353-1271-4842-806F-E436D6AF6985"
> > +#define TYPE_GUID_SYSTEM       "0FC63DAF-8483-4772-8E79-3D69D8477DE4"
> > +
> > +#define PARTS_DEFAULT \
> > +       "name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1};" \
> > +       "name=loader2,size=4MB,type=${type_guid_gpt_loader2};" \
> > +       "name=system,size=-,bootable,type=${type_guid_gpt_system};"
> > +
> > +#define CONFIG_EXTRA_ENV_SETTINGS \
> > +       "fdt_high=0xffffffffffffffff\0" \
> > +       "initrd_high=0xffffffffffffffff\0" \
> > +       "kernel_addr_r=0x84000000\0" \
> > +       "fdt_addr_r=0x88000000\0" \
> > +       "scriptaddr=0x88100000\0" \
> > +       "pxefile_addr_r=0x88200000\0" \
> > +       "ramdisk_addr_r=0x88300000\0" \
> > +       "kernel_comp_addr_r=0x90000000\0" \
> > +       "kernel_comp_size=0x4000000\0" \
> > +       "type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \
> > +       "type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
> > +       "type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
> > +       "partitions=" PARTS_DEFAULT "\0" \
> > +       BOOTENV
> > +
> > +#define CONFIG_PREBOOT \
> > +       "setenv fdt_addr ${fdtcontroladdr};" \
> > +       "fdt addr ${fdtcontroladdr};"
> > +#endif /* CONFIG_SPL_BUILD */
> > +
> > +#endif /* __SIFIVE_UNMATCHED_H */
> > --
> > 2.7.4
> >
>
> Regards,
> Bin
>
Bin Meng March 16, 2021, 3:09 a.m. UTC | #3 
Hi Green,

On Tue, Mar 16, 2021 at 10:33 AM Green Wan <green.wan@sifive.com> wrote:
>
>
>
> On Thu, Mar 11, 2021 at 10:21 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>>
>> On Thu, Mar 11, 2021 at 9:50 PM Green Wan <green.wan@sifive.com> wrote:
>> >
>> > Add dts, defconfig and board support for HiFive Unmatched.
>> >
>> > Signed-off-by: Green Wan <green.wan@sifive.com>
>> > ---
>> >  arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489 ++++++++++++++++++++
>> >  arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi    |   40 +
>> >  arch/riscv/dts/hifive-unmatched-a00.dts            |  263 ++++
>> >  board/sifive/fu540/Kconfig                         |    1 -
>> >  board/sifive/fu540/fu540.c                         |    2 +-
>>
>> It looks these fu540 changes are not needed?
>
> Let me remove the change for fu540 first and check on fu540.
>
>>
>>
>> >  board/sifive/hifive_unmatched_fu740/Kconfig        |   50 +
>> >  board/sifive/hifive_unmatched_fu740/MAINTAINERS    |    9 +
>> >  board/sifive/hifive_unmatched_fu740/Makefile       |    9 +
>>
>> >  .../hifive-unmatched-fu740.c                       |   24 +
>> >  board/sifive/hifive_unmatched_fu740/spl.c          |   85 ++
>> >  configs/sifive_hifive_unmatched_fu740_defconfig    |   57 +
>
>   I'd like to rename  "board/sifive/hifive_unmatched_fu740" to the shorter name "board/sifive/unmatched". And "configs/sifive_hifive_unmatched_fu740_defconfig" to "configs/sifive_unmatched_defconfig" in v2 patch.

Agree. I sent a patch to rename fu540 to unleashed, so that this is consistent.
http://patchwork.ozlabs.org/project/uboot/patch/20210316030622.40768-1-bmeng.cn@gmail.com/

You may rebase v2 on top of that patch.

>
>>
>> >  doc/board/sifive/fu540.rst                         |   19 +-
>>
>> here?
>>
>> >  doc/board/sifive/hifive_unmatched_fu740.rst        |  532 +++++++
>> >  drivers/reset/Kconfig                              |    2 +-
>> >  include/configs/sifive-fu540.h                     |    5 -
>>
>> and here?

Regards,
Bin
Green Wan March 16, 2021, 3:28 a.m. UTC | #4 
Thanks, Bin, will rebase it for v2 patch.

On Tue, Mar 16, 2021 at 11:09 AM Bin Meng <bmeng.cn@gmail.com> wrote:

> Hi Green,
>
> On Tue, Mar 16, 2021 at 10:33 AM Green Wan <green.wan@sifive.com> wrote:
> >
> >
> >
> > On Thu, Mar 11, 2021 at 10:21 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >>
> >> On Thu, Mar 11, 2021 at 9:50 PM Green Wan <green.wan@sifive.com> wrote:
> >> >
> >> > Add dts, defconfig and board support for HiFive Unmatched.
> >> >
> >> > Signed-off-by: Green Wan <green.wan@sifive.com>
> >> > ---
> >> >  arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi | 1489
> ++++++++++++++++++++
> >> >  arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi    |   40 +
> >> >  arch/riscv/dts/hifive-unmatched-a00.dts            |  263 ++++
> >> >  board/sifive/fu540/Kconfig                         |    1 -
> >> >  board/sifive/fu540/fu540.c                         |    2 +-
> >>
> >> It looks these fu540 changes are not needed?
> >
> > Let me remove the change for fu540 first and check on fu540.
> >
> >>
> >>
> >> >  board/sifive/hifive_unmatched_fu740/Kconfig        |   50 +
> >> >  board/sifive/hifive_unmatched_fu740/MAINTAINERS    |    9 +
> >> >  board/sifive/hifive_unmatched_fu740/Makefile       |    9 +
> >>
> >> >  .../hifive-unmatched-fu740.c                       |   24 +
> >> >  board/sifive/hifive_unmatched_fu740/spl.c          |   85 ++
> >> >  configs/sifive_hifive_unmatched_fu740_defconfig    |   57 +
> >
> >   I'd like to rename  "board/sifive/hifive_unmatched_fu740" to the
> shorter name "board/sifive/unmatched". And
> "configs/sifive_hifive_unmatched_fu740_defconfig" to
> "configs/sifive_unmatched_defconfig" in v2 patch.
>
> Agree. I sent a patch to rename fu540 to unleashed, so that this is
> consistent.
>
> http://patchwork.ozlabs.org/project/uboot/patch/20210316030622.40768-1-bmeng.cn@gmail.com/
>
> You may rebase v2 on top of that patch.
>
> >
> >>
> >> >  doc/board/sifive/fu540.rst                         |   19 +-
> >>
> >> here?
> >>
> >> >  doc/board/sifive/hifive_unmatched_fu740.rst        |  532 +++++++
> >> >  drivers/reset/Kconfig                              |    2 +-
> >> >  include/configs/sifive-fu540.h                     |    5 -
> >>
> >> and here?
>
> Regards,
> Bin
>
diff mbox series

Patch

diff --git a/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
new file mode 100644
index 0000000..4209491
--- /dev/null
+++ b/arch/riscv/dts/fu740-hifive-unmatched-a00-ddr.dtsi
@@ -0,0 +1,1489 @@ 
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * (C) Copyright 2020-2021 SiFive, Inc
+ */
+
+&dmc {
+	sifive,ddr-params = <
+		0x00000a00 /* DENALI_CTL_00_DATA */
+		0x00000000 /* DENALI_CTL_01_DATA */
+		0x00000000 /* DENALI_CTL_02_DATA */
+		0x00000000 /* DENALI_CTL_03_DATA */
+		0x00000000 /* DENALI_CTL_04_DATA */
+		0x00000000 /* DENALI_CTL_05_DATA */
+		0x0000000a /* DENALI_CTL_06_DATA */
+		0x0002d362 /* DENALI_CTL_07_DATA */
+		0x00071073 /* DENALI_CTL_08_DATA */
+		0x0a1c0255 /* DENALI_CTL_09_DATA */
+		0x1c1c0400 /* DENALI_CTL_10_DATA */
+		0x0404c90b /* DENALI_CTL_11_DATA */
+		0x2b050405 /* DENALI_CTL_12_DATA */
+		0x0d0c081e /* DENALI_CTL_13_DATA */
+		0x08090914 /* DENALI_CTL_14_DATA */
+		0x00fde718 /* DENALI_CTL_15_DATA */
+		0x00180a05 /* DENALI_CTL_16_DATA */
+		0x008b130d /* DENALI_CTL_17_DATA */
+		0x01000118 /* DENALI_CTL_18_DATA */
+		0x0d032001 /* DENALI_CTL_19_DATA */
+		0x00000000 /* DENALI_CTL_20_DATA */
+		0x00000101 /* DENALI_CTL_21_DATA */
+		0x00000000 /* DENALI_CTL_22_DATA */
+		0x0a000000 /* DENALI_CTL_23_DATA */
+		0x00000000 /* DENALI_CTL_24_DATA */
+		0x01450100 /* DENALI_CTL_25_DATA */
+		0x00001c36 /* DENALI_CTL_26_DATA */
+		0x00000005 /* DENALI_CTL_27_DATA */
+		0x00170006 /* DENALI_CTL_28_DATA */
+		0x014e0400 /* DENALI_CTL_29_DATA */
+		0x03010000 /* DENALI_CTL_30_DATA */
+		0x000a0e00 /* DENALI_CTL_31_DATA */
+		0x04030200 /* DENALI_CTL_32_DATA */
+		0x0000031f /* DENALI_CTL_33_DATA */
+		0x00070004 /* DENALI_CTL_34_DATA */
+		0x00000000 /* DENALI_CTL_35_DATA */
+		0x00000000 /* DENALI_CTL_36_DATA */
+		0x00000000 /* DENALI_CTL_37_DATA */
+		0x00000000 /* DENALI_CTL_38_DATA */
+		0x00000000 /* DENALI_CTL_39_DATA */
+		0x00000000 /* DENALI_CTL_40_DATA */
+		0x00000000 /* DENALI_CTL_41_DATA */
+		0x00000000 /* DENALI_CTL_42_DATA */
+		0x00000000 /* DENALI_CTL_43_DATA */
+		0x00000000 /* DENALI_CTL_44_DATA */
+		0x00000000 /* DENALI_CTL_45_DATA */
+		0x00000000 /* DENALI_CTL_46_DATA */
+		0x00000000 /* DENALI_CTL_47_DATA */
+		0x00000000 /* DENALI_CTL_48_DATA */
+		0x00000000 /* DENALI_CTL_49_DATA */
+		0x00000000 /* DENALI_CTL_50_DATA */
+		0x00000000 /* DENALI_CTL_51_DATA */
+		0x00000000 /* DENALI_CTL_52_DATA */
+		0x00000000 /* DENALI_CTL_53_DATA */
+		0x00000000 /* DENALI_CTL_54_DATA */
+		0x00000000 /* DENALI_CTL_55_DATA */
+		0x00000000 /* DENALI_CTL_56_DATA */
+		0x00000000 /* DENALI_CTL_57_DATA */
+		0x00000000 /* DENALI_CTL_58_DATA */
+		0x00000000 /* DENALI_CTL_59_DATA */
+		0x00000424 /* DENALI_CTL_60_DATA */
+		0x00000201 /* DENALI_CTL_61_DATA */
+		0x00001008 /* DENALI_CTL_62_DATA */
+		0x00000000 /* DENALI_CTL_63_DATA */
+		0x00000200 /* DENALI_CTL_64_DATA */
+		0x00000800 /* DENALI_CTL_65_DATA */
+		0x00000481 /* DENALI_CTL_66_DATA */
+		0x00000400 /* DENALI_CTL_67_DATA */
+		0x00000424 /* DENALI_CTL_68_DATA */
+		0x00000201 /* DENALI_CTL_69_DATA */
+		0x00001008 /* DENALI_CTL_70_DATA */
+		0x00000000 /* DENALI_CTL_71_DATA */
+		0x00000200 /* DENALI_CTL_72_DATA */
+		0x00000800 /* DENALI_CTL_73_DATA */
+		0x00000481 /* DENALI_CTL_74_DATA */
+		0x00000400 /* DENALI_CTL_75_DATA */
+		0x01010000 /* DENALI_CTL_76_DATA */
+		0x00000000 /* DENALI_CTL_77_DATA */
+		0x00000000 /* DENALI_CTL_78_DATA */
+		0x00000000 /* DENALI_CTL_79_DATA */
+		0x00000000 /* DENALI_CTL_80_DATA */
+		0x00000000 /* DENALI_CTL_81_DATA */
+		0x00000000 /* DENALI_CTL_82_DATA */
+		0x00000000 /* DENALI_CTL_83_DATA */
+		0x00000000 /* DENALI_CTL_84_DATA */
+		0x00000000 /* DENALI_CTL_85_DATA */
+		0x00000000 /* DENALI_CTL_86_DATA */
+		0x00000000 /* DENALI_CTL_87_DATA */
+		0x00000000 /* DENALI_CTL_88_DATA */
+		0x00000000 /* DENALI_CTL_89_DATA */
+		0x00000000 /* DENALI_CTL_90_DATA */
+		0x00000000 /* DENALI_CTL_91_DATA */
+		0x00000000 /* DENALI_CTL_92_DATA */
+		0x00000000 /* DENALI_CTL_93_DATA */
+		0x00000000 /* DENALI_CTL_94_DATA */
+		0x00000000 /* DENALI_CTL_95_DATA */
+		0x00000000 /* DENALI_CTL_96_DATA */
+		0x00000000 /* DENALI_CTL_97_DATA */
+		0x00000000 /* DENALI_CTL_98_DATA */
+		0x00000000 /* DENALI_CTL_99_DATA */
+		0x00000000 /* DENALI_CTL_100_DATA */
+		0x00000000 /* DENALI_CTL_101_DATA */
+		0x00000000 /* DENALI_CTL_102_DATA */
+		0x00000000 /* DENALI_CTL_103_DATA */
+		0x00000000 /* DENALI_CTL_104_DATA */
+		0x00000003 /* DENALI_CTL_105_DATA */
+		0x00000000 /* DENALI_CTL_106_DATA */
+		0x00000000 /* DENALI_CTL_107_DATA */
+		0x00000000 /* DENALI_CTL_108_DATA */
+		0x00000000 /* DENALI_CTL_109_DATA */
+		0x01000000 /* DENALI_CTL_110_DATA */
+		0x00040000 /* DENALI_CTL_111_DATA */
+		0x00800200 /* DENALI_CTL_112_DATA */
+		0x00000200 /* DENALI_CTL_113_DATA */
+		0x00000040 /* DENALI_CTL_114_DATA */
+		0x01000100 /* DENALI_CTL_115_DATA */
+		0x0a000002 /* DENALI_CTL_116_DATA */
+		0x0101ffff /* DENALI_CTL_117_DATA */
+		0x01010101 /* DENALI_CTL_118_DATA */
+		0x01010101 /* DENALI_CTL_119_DATA */
+		0x0000010b /* DENALI_CTL_120_DATA */
+		0x00000c03 /* DENALI_CTL_121_DATA */
+		0x00000000 /* DENALI_CTL_122_DATA */
+		0x00000000 /* DENALI_CTL_123_DATA */
+		0x00000000 /* DENALI_CTL_124_DATA */
+		0x00000000 /* DENALI_CTL_125_DATA */
+		0x00030300 /* DENALI_CTL_126_DATA */
+		0x00000000 /* DENALI_CTL_127_DATA */
+		0x00010101 /* DENALI_CTL_128_DATA */
+		0x00000000 /* DENALI_CTL_129_DATA */
+		0x00000000 /* DENALI_CTL_130_DATA */
+		0x00000000 /* DENALI_CTL_131_DATA */
+		0x00000000 /* DENALI_CTL_132_DATA */
+		0x00000000 /* DENALI_CTL_133_DATA */
+		0x00000000 /* DENALI_CTL_134_DATA */
+		0x00000000 /* DENALI_CTL_135_DATA */
+		0x00000000 /* DENALI_CTL_136_DATA */
+		0x00000000 /* DENALI_CTL_137_DATA */
+		0x00000000 /* DENALI_CTL_138_DATA */
+		0x00000000 /* DENALI_CTL_139_DATA */
+		0x00000000 /* DENALI_CTL_140_DATA */
+		0x00000000 /* DENALI_CTL_141_DATA */
+		0x00000000 /* DENALI_CTL_142_DATA */
+		0x00000000 /* DENALI_CTL_143_DATA */
+		0x00000000 /* DENALI_CTL_144_DATA */
+		0x00000000 /* DENALI_CTL_145_DATA */
+		0x00000000 /* DENALI_CTL_146_DATA */
+		0x00000000 /* DENALI_CTL_147_DATA */
+		0x00000000 /* DENALI_CTL_148_DATA */
+		0x00000000 /* DENALI_CTL_149_DATA */
+		0x00000000 /* DENALI_CTL_150_DATA */
+		0x00000000 /* DENALI_CTL_151_DATA */
+		0x00000000 /* DENALI_CTL_152_DATA */
+		0x00000000 /* DENALI_CTL_153_DATA */
+		0x00000000 /* DENALI_CTL_154_DATA */
+		0x00000000 /* DENALI_CTL_155_DATA */
+		0x00000000 /* DENALI_CTL_156_DATA */
+		0x00000000 /* DENALI_CTL_157_DATA */
+		0x00000000 /* DENALI_CTL_158_DATA */
+		0x00000000 /* DENALI_CTL_159_DATA */
+		0x00000000 /* DENALI_CTL_160_DATA */
+		0x02010102 /* DENALI_CTL_161_DATA */
+		0x0108070d /* DENALI_CTL_162_DATA */
+		0x05050300 /* DENALI_CTL_163_DATA */
+		0x04000503 /* DENALI_CTL_164_DATA */
+		0x00000000 /* DENALI_CTL_165_DATA */
+		0x00000000 /* DENALI_CTL_166_DATA */
+		0x00000000 /* DENALI_CTL_167_DATA */
+		0x00000000 /* DENALI_CTL_168_DATA */
+		0x280d0000 /* DENALI_CTL_169_DATA */
+		0x01000000 /* DENALI_CTL_170_DATA */
+		0x00000000 /* DENALI_CTL_171_DATA */
+		0x00030001 /* DENALI_CTL_172_DATA */
+		0x00000000 /* DENALI_CTL_173_DATA */
+		0x00000000 /* DENALI_CTL_174_DATA */
+		0x00000000 /* DENALI_CTL_175_DATA */
+		0x00000000 /* DENALI_CTL_176_DATA */
+		0x00000000 /* DENALI_CTL_177_DATA */
+		0x00000000 /* DENALI_CTL_178_DATA */
+		0x00000000 /* DENALI_CTL_179_DATA */
+		0x00000000 /* DENALI_CTL_180_DATA */
+		0x01000000 /* DENALI_CTL_181_DATA */
+		0x00000001 /* DENALI_CTL_182_DATA */
+		0x00000100 /* DENALI_CTL_183_DATA */
+		0x00010303 /* DENALI_CTL_184_DATA */
+		0x67676701 /* DENALI_CTL_185_DATA */
+		0x67676767 /* DENALI_CTL_186_DATA */
+		0x67676767 /* DENALI_CTL_187_DATA */
+		0x67676767 /* DENALI_CTL_188_DATA */
+		0x67676767 /* DENALI_CTL_189_DATA */
+		0x67676767 /* DENALI_CTL_190_DATA */
+		0x67676767 /* DENALI_CTL_191_DATA */
+		0x67676767 /* DENALI_CTL_192_DATA */
+		0x67676767 /* DENALI_CTL_193_DATA */
+		0x01000067 /* DENALI_CTL_194_DATA */
+		0x00000001 /* DENALI_CTL_195_DATA */
+		0x00000101 /* DENALI_CTL_196_DATA */
+		0x00000000 /* DENALI_CTL_197_DATA */
+		0x00000000 /* DENALI_CTL_198_DATA */
+		0x00000000 /* DENALI_CTL_199_DATA */
+		0x00000000 /* DENALI_CTL_200_DATA */
+		0x00000000 /* DENALI_CTL_201_DATA */
+		0x00000000 /* DENALI_CTL_202_DATA */
+		0x00000000 /* DENALI_CTL_203_DATA */
+		0x00000000 /* DENALI_CTL_204_DATA */
+		0x00000000 /* DENALI_CTL_205_DATA */
+		0x00000000 /* DENALI_CTL_206_DATA */
+		0x00000000 /* DENALI_CTL_207_DATA */
+		0x00000001 /* DENALI_CTL_208_DATA */
+		0x00000000 /* DENALI_CTL_209_DATA */
+		0x007fffff /* DENALI_CTL_210_DATA */
+		0x00000000 /* DENALI_CTL_211_DATA */
+		0x007fffff /* DENALI_CTL_212_DATA */
+		0x00000000 /* DENALI_CTL_213_DATA */
+		0x007fffff /* DENALI_CTL_214_DATA */
+		0x00000000 /* DENALI_CTL_215_DATA */
+		0x007fffff /* DENALI_CTL_216_DATA */
+		0x00000000 /* DENALI_CTL_217_DATA */
+		0x007fffff /* DENALI_CTL_218_DATA */
+		0x00000000 /* DENALI_CTL_219_DATA */
+		0x007fffff /* DENALI_CTL_220_DATA */
+		0x00000000 /* DENALI_CTL_221_DATA */
+		0x007fffff /* DENALI_CTL_222_DATA */
+		0x00000000 /* DENALI_CTL_223_DATA */
+		0x037fffff /* DENALI_CTL_224_DATA */
+		0xffffffff /* DENALI_CTL_225_DATA */
+		0x000f000f /* DENALI_CTL_226_DATA */
+		0x00ffff03 /* DENALI_CTL_227_DATA */
+		0x000fffff /* DENALI_CTL_228_DATA */
+		0x0003000f /* DENALI_CTL_229_DATA */
+		0xffffffff /* DENALI_CTL_230_DATA */
+		0x000f000f /* DENALI_CTL_231_DATA */
+		0x00ffff03 /* DENALI_CTL_232_DATA */
+		0x000fffff /* DENALI_CTL_233_DATA */
+		0x0003000f /* DENALI_CTL_234_DATA */
+		0xffffffff /* DENALI_CTL_235_DATA */
+		0x000f000f /* DENALI_CTL_236_DATA */
+		0x00ffff03 /* DENALI_CTL_237_DATA */
+		0x000fffff /* DENALI_CTL_238_DATA */
+		0x0003000f /* DENALI_CTL_239_DATA */
+		0xffffffff /* DENALI_CTL_240_DATA */
+		0x000f000f /* DENALI_CTL_241_DATA */
+		0x00ffff03 /* DENALI_CTL_242_DATA */
+		0x000fffff /* DENALI_CTL_243_DATA */
+		0x6407000f /* DENALI_CTL_244_DATA */
+		0x01640001 /* DENALI_CTL_245_DATA */
+		0x00000000 /* DENALI_CTL_246_DATA */
+		0x00000000 /* DENALI_CTL_247_DATA */
+		0x00001800 /* DENALI_CTL_248_DATA */
+		0x00386c05 /* DENALI_CTL_249_DATA */
+		0x02000200 /* DENALI_CTL_250_DATA */
+		0x02000200 /* DENALI_CTL_251_DATA */
+		0x0000386c /* DENALI_CTL_252_DATA */
+		0x00023438 /* DENALI_CTL_253_DATA */
+		0x02020d0f /* DENALI_CTL_254_DATA */
+		0x00140303 /* DENALI_CTL_255_DATA */
+		0x00000000 /* DENALI_CTL_256_DATA */
+		0x00000000 /* DENALI_CTL_257_DATA */
+		0x00001403 /* DENALI_CTL_258_DATA */
+		0x00000000 /* DENALI_CTL_259_DATA */
+		0x00000000 /* DENALI_CTL_260_DATA */
+		0x00000000 /* DENALI_CTL_261_DATA */
+		0x00000000 /* DENALI_CTL_262_DATA */
+		0x0c010000 /* DENALI_CTL_263_DATA */
+		0x00000008 /* DENALI_CTL_264_DATA */
+		0x01375642 /* DENALI_PHY_00_DATA */
+		0x0004c008 /* DENALI_PHY_01_DATA */
+		0x000000da /* DENALI_PHY_02_DATA */
+		0x00000000 /* DENALI_PHY_03_DATA */
+		0x00000000 /* DENALI_PHY_04_DATA */
+		0x00010000 /* DENALI_PHY_05_DATA */
+		0x01DDDD90 /* DENALI_PHY_06_DATA */
+		0x01DDDD90 /* DENALI_PHY_07_DATA */
+		0x01030001 /* DENALI_PHY_08_DATA */
+		0x01000000 /* DENALI_PHY_09_DATA */
+		0x00c00000 /* DENALI_PHY_10_DATA */
+		0x00000007 /* DENALI_PHY_11_DATA */
+		0x00000000 /* DENALI_PHY_12_DATA */
+		0x00000000 /* DENALI_PHY_13_DATA */
+		0x04000408 /* DENALI_PHY_14_DATA */
+		0x00000408 /* DENALI_PHY_15_DATA */
+		0x00e4e400 /* DENALI_PHY_16_DATA */
+		0x00000000 /* DENALI_PHY_17_DATA */
+		0x00000000 /* DENALI_PHY_18_DATA */
+		0x00000000 /* DENALI_PHY_19_DATA */
+		0x00000000 /* DENALI_PHY_20_DATA */
+		0x00000000 /* DENALI_PHY_21_DATA */
+		0x00000000 /* DENALI_PHY_22_DATA */
+		0x00000000 /* DENALI_PHY_23_DATA */
+		0x00000000 /* DENALI_PHY_24_DATA */
+		0x00000000 /* DENALI_PHY_25_DATA */
+		0x00000000 /* DENALI_PHY_26_DATA */
+		0x00000000 /* DENALI_PHY_27_DATA */
+		0x00000000 /* DENALI_PHY_28_DATA */
+		0x00000000 /* DENALI_PHY_29_DATA */
+		0x00000000 /* DENALI_PHY_30_DATA */
+		0x00000000 /* DENALI_PHY_31_DATA */
+		0x00000000 /* DENALI_PHY_32_DATA */
+		0x00200000 /* DENALI_PHY_33_DATA */
+		0x00000000 /* DENALI_PHY_34_DATA */
+		0x00000000 /* DENALI_PHY_35_DATA */
+		0x00000000 /* DENALI_PHY_36_DATA */
+		0x00000000 /* DENALI_PHY_37_DATA */
+		0x00000000 /* DENALI_PHY_38_DATA */
+		0x00000000 /* DENALI_PHY_39_DATA */
+		0x02800280 /* DENALI_PHY_40_DATA */
+		0x02800280 /* DENALI_PHY_41_DATA */
+		0x02800280 /* DENALI_PHY_42_DATA */
+		0x02800280 /* DENALI_PHY_43_DATA */
+		0x00000280 /* DENALI_PHY_44_DATA */
+		0x00000000 /* DENALI_PHY_45_DATA */
+		0x00000000 /* DENALI_PHY_46_DATA */
+		0x00000000 /* DENALI_PHY_47_DATA */
+		0x00000000 /* DENALI_PHY_48_DATA */
+		0x00000000 /* DENALI_PHY_49_DATA */
+		0x00800080 /* DENALI_PHY_50_DATA */
+		0x00800080 /* DENALI_PHY_51_DATA */
+		0x00800080 /* DENALI_PHY_52_DATA */
+		0x00800080 /* DENALI_PHY_53_DATA */
+		0x00800080 /* DENALI_PHY_54_DATA */
+		0x00800080 /* DENALI_PHY_55_DATA */
+		0x00800080 /* DENALI_PHY_56_DATA */
+		0x00800080 /* DENALI_PHY_57_DATA */
+		0x00800080 /* DENALI_PHY_58_DATA */
+		0x000100da /* DENALI_PHY_59_DATA */
+		0x01ff0010 /* DENALI_PHY_60_DATA */
+		0x00000000 /* DENALI_PHY_61_DATA */
+		0x00000000 /* DENALI_PHY_62_DATA */
+		0x00000002 /* DENALI_PHY_63_DATA */
+		0x51313152 /* DENALI_PHY_64_DATA */
+		0x80013130 /* DENALI_PHY_65_DATA */
+		0x02000080 /* DENALI_PHY_66_DATA */
+		0x00100001 /* DENALI_PHY_67_DATA */
+		0x0c064208 /* DENALI_PHY_68_DATA */
+		0x000f0c0f /* DENALI_PHY_69_DATA */
+		0x01000140 /* DENALI_PHY_70_DATA */
+		0x0000000c /* DENALI_PHY_71_DATA */
+		0x00000000 /* DENALI_PHY_72_DATA */
+		0x00000000 /* DENALI_PHY_73_DATA */
+		0x00000000 /* DENALI_PHY_74_DATA */
+		0x00000000 /* DENALI_PHY_75_DATA */
+		0x00000000 /* DENALI_PHY_76_DATA */
+		0x00000000 /* DENALI_PHY_77_DATA */
+		0x00000000 /* DENALI_PHY_78_DATA */
+		0x00000000 /* DENALI_PHY_79_DATA */
+		0x00000000 /* DENALI_PHY_80_DATA */
+		0x00000000 /* DENALI_PHY_81_DATA */
+		0x00000000 /* DENALI_PHY_82_DATA */
+		0x00000000 /* DENALI_PHY_83_DATA */
+		0x00000000 /* DENALI_PHY_84_DATA */
+		0x00000000 /* DENALI_PHY_85_DATA */
+		0x00000000 /* DENALI_PHY_86_DATA */
+		0x00000000 /* DENALI_PHY_87_DATA */
+		0x00000000 /* DENALI_PHY_88_DATA */
+		0x00000000 /* DENALI_PHY_89_DATA */
+		0x00000000 /* DENALI_PHY_90_DATA */
+		0x00000000 /* DENALI_PHY_91_DATA */
+		0x00000000 /* DENALI_PHY_92_DATA */
+		0x00000000 /* DENALI_PHY_93_DATA */
+		0x00000000 /* DENALI_PHY_94_DATA */
+		0x00000000 /* DENALI_PHY_95_DATA */
+		0x00000000 /* DENALI_PHY_96_DATA */
+		0x00000000 /* DENALI_PHY_97_DATA */
+		0x00000000 /* DENALI_PHY_98_DATA */
+		0x00000000 /* DENALI_PHY_99_DATA */
+		0x00000000 /* DENALI_PHY_100_DATA */
+		0x00000000 /* DENALI_PHY_101_DATA */
+		0x00000000 /* DENALI_PHY_102_DATA */
+		0x00000000 /* DENALI_PHY_103_DATA */
+		0x00000000 /* DENALI_PHY_104_DATA */
+		0x00000000 /* DENALI_PHY_105_DATA */
+		0x00000000 /* DENALI_PHY_106_DATA */
+		0x00000000 /* DENALI_PHY_107_DATA */
+		0x00000000 /* DENALI_PHY_108_DATA */
+		0x00000000 /* DENALI_PHY_109_DATA */
+		0x00000000 /* DENALI_PHY_110_DATA */
+		0x00000000 /* DENALI_PHY_111_DATA */
+		0x00000000 /* DENALI_PHY_112_DATA */
+		0x00000000 /* DENALI_PHY_113_DATA */
+		0x00000000 /* DENALI_PHY_114_DATA */
+		0x00000000 /* DENALI_PHY_115_DATA */
+		0x00000000 /* DENALI_PHY_116_DATA */
+		0x00000000 /* DENALI_PHY_117_DATA */
+		0x00000000 /* DENALI_PHY_118_DATA */
+		0x00000000 /* DENALI_PHY_119_DATA */
+		0x00000000 /* DENALI_PHY_120_DATA */
+		0x00000000 /* DENALI_PHY_121_DATA */
+		0x00000000 /* DENALI_PHY_122_DATA */
+		0x00000000 /* DENALI_PHY_123_DATA */
+		0x00000000 /* DENALI_PHY_124_DATA */
+		0x00000000 /* DENALI_PHY_125_DATA */
+		0x00000000 /* DENALI_PHY_126_DATA */
+		0x00000000 /* DENALI_PHY_127_DATA */
+		0x40263571 /* DENALI_PHY_128_DATA */
+		0x0004c008 /* DENALI_PHY_129_DATA */
+		0x000000da /* DENALI_PHY_130_DATA */
+		0x00000000 /* DENALI_PHY_131_DATA */
+		0x00000000 /* DENALI_PHY_132_DATA */
+		0x00010000 /* DENALI_PHY_133_DATA */
+		0x01DDDD90 /* DENALI_PHY_134_DATA */
+		0x01DDDD90 /* DENALI_PHY_135_DATA */
+		0x01030001 /* DENALI_PHY_136_DATA */
+		0x01000000 /* DENALI_PHY_137_DATA */
+		0x00c00000 /* DENALI_PHY_138_DATA */
+		0x00000007 /* DENALI_PHY_139_DATA */
+		0x00000000 /* DENALI_PHY_140_DATA */
+		0x00000000 /* DENALI_PHY_141_DATA */
+		0x04000408 /* DENALI_PHY_142_DATA */
+		0x00000408 /* DENALI_PHY_143_DATA */
+		0x00e4e400 /* DENALI_PHY_144_DATA */
+		0x00000000 /* DENALI_PHY_145_DATA */
+		0x00000000 /* DENALI_PHY_146_DATA */
+		0x00000000 /* DENALI_PHY_147_DATA */
+		0x00000000 /* DENALI_PHY_148_DATA */
+		0x00000000 /* DENALI_PHY_149_DATA */
+		0x00000000 /* DENALI_PHY_150_DATA */
+		0x00000000 /* DENALI_PHY_151_DATA */
+		0x00000000 /* DENALI_PHY_152_DATA */
+		0x00000000 /* DENALI_PHY_153_DATA */
+		0x00000000 /* DENALI_PHY_154_DATA */
+		0x00000000 /* DENALI_PHY_155_DATA */
+		0x00000000 /* DENALI_PHY_156_DATA */
+		0x00000000 /* DENALI_PHY_157_DATA */
+		0x00000000 /* DENALI_PHY_158_DATA */
+		0x00000000 /* DENALI_PHY_159_DATA */
+		0x00000000 /* DENALI_PHY_160_DATA */
+		0x00200000 /* DENALI_PHY_161_DATA */
+		0x00000000 /* DENALI_PHY_162_DATA */
+		0x00000000 /* DENALI_PHY_163_DATA */
+		0x00000000 /* DENALI_PHY_164_DATA */
+		0x00000000 /* DENALI_PHY_165_DATA */
+		0x00000000 /* DENALI_PHY_166_DATA */
+		0x00000000 /* DENALI_PHY_167_DATA */
+		0x02800280 /* DENALI_PHY_168_DATA */
+		0x02800280 /* DENALI_PHY_169_DATA */
+		0x02800280 /* DENALI_PHY_170_DATA */
+		0x02800280 /* DENALI_PHY_171_DATA */
+		0x00000280 /* DENALI_PHY_172_DATA */
+		0x00000000 /* DENALI_PHY_173_DATA */
+		0x00000000 /* DENALI_PHY_174_DATA */
+		0x00000000 /* DENALI_PHY_175_DATA */
+		0x00000000 /* DENALI_PHY_176_DATA */
+		0x00000000 /* DENALI_PHY_177_DATA */
+		0x00800080 /* DENALI_PHY_178_DATA */
+		0x00800080 /* DENALI_PHY_179_DATA */
+		0x00800080 /* DENALI_PHY_180_DATA */
+		0x00800080 /* DENALI_PHY_181_DATA */
+		0x00800080 /* DENALI_PHY_182_DATA */
+		0x00800080 /* DENALI_PHY_183_DATA */
+		0x00800080 /* DENALI_PHY_184_DATA */
+		0x00800080 /* DENALI_PHY_185_DATA */
+		0x00800080 /* DENALI_PHY_186_DATA */
+		0x000100da /* DENALI_PHY_187_DATA */
+		0x01ff0010 /* DENALI_PHY_188_DATA */
+		0x00000000 /* DENALI_PHY_189_DATA */
+		0x00000000 /* DENALI_PHY_190_DATA */
+		0x00000002 /* DENALI_PHY_191_DATA */
+		0x51313152 /* DENALI_PHY_192_DATA */
+		0x80013130 /* DENALI_PHY_193_DATA */
+		0x02000080 /* DENALI_PHY_194_DATA */
+		0x00100001 /* DENALI_PHY_195_DATA */
+		0x0c064208 /* DENALI_PHY_196_DATA */
+		0x000f0c0f /* DENALI_PHY_197_DATA */
+		0x01000140 /* DENALI_PHY_198_DATA */
+		0x0000000c /* DENALI_PHY_199_DATA */
+		0x00000000 /* DENALI_PHY_200_DATA */
+		0x00000000 /* DENALI_PHY_201_DATA */
+		0x00000000 /* DENALI_PHY_202_DATA */
+		0x00000000 /* DENALI_PHY_203_DATA */
+		0x00000000 /* DENALI_PHY_204_DATA */
+		0x00000000 /* DENALI_PHY_205_DATA */
+		0x00000000 /* DENALI_PHY_206_DATA */
+		0x00000000 /* DENALI_PHY_207_DATA */
+		0x00000000 /* DENALI_PHY_208_DATA */
+		0x00000000 /* DENALI_PHY_209_DATA */
+		0x00000000 /* DENALI_PHY_210_DATA */
+		0x00000000 /* DENALI_PHY_211_DATA */
+		0x00000000 /* DENALI_PHY_212_DATA */
+		0x00000000 /* DENALI_PHY_213_DATA */
+		0x00000000 /* DENALI_PHY_214_DATA */
+		0x00000000 /* DENALI_PHY_215_DATA */
+		0x00000000 /* DENALI_PHY_216_DATA */
+		0x00000000 /* DENALI_PHY_217_DATA */
+		0x00000000 /* DENALI_PHY_218_DATA */
+		0x00000000 /* DENALI_PHY_219_DATA */
+		0x00000000 /* DENALI_PHY_220_DATA */
+		0x00000000 /* DENALI_PHY_221_DATA */
+		0x00000000 /* DENALI_PHY_222_DATA */
+		0x00000000 /* DENALI_PHY_223_DATA */
+		0x00000000 /* DENALI_PHY_224_DATA */
+		0x00000000 /* DENALI_PHY_225_DATA */
+		0x00000000 /* DENALI_PHY_226_DATA */
+		0x00000000 /* DENALI_PHY_227_DATA */
+		0x00000000 /* DENALI_PHY_228_DATA */
+		0x00000000 /* DENALI_PHY_229_DATA */
+		0x00000000 /* DENALI_PHY_230_DATA */
+		0x00000000 /* DENALI_PHY_231_DATA */
+		0x00000000 /* DENALI_PHY_232_DATA */
+		0x00000000 /* DENALI_PHY_233_DATA */
+		0x00000000 /* DENALI_PHY_234_DATA */
+		0x00000000 /* DENALI_PHY_235_DATA */
+		0x00000000 /* DENALI_PHY_236_DATA */
+		0x00000000 /* DENALI_PHY_237_DATA */
+		0x00000000 /* DENALI_PHY_238_DATA */
+		0x00000000 /* DENALI_PHY_239_DATA */
+		0x00000000 /* DENALI_PHY_240_DATA */
+		0x00000000 /* DENALI_PHY_241_DATA */
+		0x00000000 /* DENALI_PHY_242_DATA */
+		0x00000000 /* DENALI_PHY_243_DATA */
+		0x00000000 /* DENALI_PHY_244_DATA */
+		0x00000000 /* DENALI_PHY_245_DATA */
+		0x00000000 /* DENALI_PHY_246_DATA */
+		0x00000000 /* DENALI_PHY_247_DATA */
+		0x00000000 /* DENALI_PHY_248_DATA */
+		0x00000000 /* DENALI_PHY_249_DATA */
+		0x00000000 /* DENALI_PHY_250_DATA */
+		0x00000000 /* DENALI_PHY_251_DATA */
+		0x00000000 /* DENALI_PHY_252_DATA */
+		0x00000000 /* DENALI_PHY_253_DATA */
+		0x00000000 /* DENALI_PHY_254_DATA */
+		0x00000000 /* DENALI_PHY_255_DATA */
+		0x46052371 /* DENALI_PHY_256_DATA */
+		0x0004c008 /* DENALI_PHY_257_DATA */
+		0x000000da /* DENALI_PHY_258_DATA */
+		0x00000000 /* DENALI_PHY_259_DATA */
+		0x00000000 /* DENALI_PHY_260_DATA */
+		0x00010000 /* DENALI_PHY_261_DATA */
+		0x01DDDD90 /* DENALI_PHY_262_DATA */
+		0x01DDDD90 /* DENALI_PHY_263_DATA */
+		0x01030001 /* DENALI_PHY_264_DATA */
+		0x01000000 /* DENALI_PHY_265_DATA */
+		0x00c00000 /* DENALI_PHY_266_DATA */
+		0x00000007 /* DENALI_PHY_267_DATA */
+		0x00000000 /* DENALI_PHY_268_DATA */
+		0x00000000 /* DENALI_PHY_269_DATA */
+		0x04000408 /* DENALI_PHY_270_DATA */
+		0x00000408 /* DENALI_PHY_271_DATA */
+		0x00e4e400 /* DENALI_PHY_272_DATA */
+		0x00000000 /* DENALI_PHY_273_DATA */
+		0x00000000 /* DENALI_PHY_274_DATA */
+		0x00000000 /* DENALI_PHY_275_DATA */
+		0x00000000 /* DENALI_PHY_276_DATA */
+		0x00000000 /* DENALI_PHY_277_DATA */
+		0x00000000 /* DENALI_PHY_278_DATA */
+		0x00000000 /* DENALI_PHY_279_DATA */
+		0x00000000 /* DENALI_PHY_280_DATA */
+		0x00000000 /* DENALI_PHY_281_DATA */
+		0x00000000 /* DENALI_PHY_282_DATA */
+		0x00000000 /* DENALI_PHY_283_DATA */
+		0x00000000 /* DENALI_PHY_284_DATA */
+		0x00000000 /* DENALI_PHY_285_DATA */
+		0x00000000 /* DENALI_PHY_286_DATA */
+		0x00000000 /* DENALI_PHY_287_DATA */
+		0x00000000 /* DENALI_PHY_288_DATA */
+		0x00200000 /* DENALI_PHY_289_DATA */
+		0x00000000 /* DENALI_PHY_290_DATA */
+		0x00000000 /* DENALI_PHY_291_DATA */
+		0x00000000 /* DENALI_PHY_292_DATA */
+		0x00000000 /* DENALI_PHY_293_DATA */
+		0x00000000 /* DENALI_PHY_294_DATA */
+		0x00000000 /* DENALI_PHY_295_DATA */
+		0x02800280 /* DENALI_PHY_296_DATA */
+		0x02800280 /* DENALI_PHY_297_DATA */
+		0x02800280 /* DENALI_PHY_298_DATA */
+		0x02800280 /* DENALI_PHY_299_DATA */
+		0x00000280 /* DENALI_PHY_300_DATA */
+		0x00000000 /* DENALI_PHY_301_DATA */
+		0x00000000 /* DENALI_PHY_302_DATA */
+		0x00000000 /* DENALI_PHY_303_DATA */
+		0x00000000 /* DENALI_PHY_304_DATA */
+		0x00000000 /* DENALI_PHY_305_DATA */
+		0x00800080 /* DENALI_PHY_306_DATA */
+		0x00800080 /* DENALI_PHY_307_DATA */
+		0x00800080 /* DENALI_PHY_308_DATA */
+		0x00800080 /* DENALI_PHY_309_DATA */
+		0x00800080 /* DENALI_PHY_310_DATA */
+		0x00800080 /* DENALI_PHY_311_DATA */
+		0x00800080 /* DENALI_PHY_312_DATA */
+		0x00800080 /* DENALI_PHY_313_DATA */
+		0x00800080 /* DENALI_PHY_314_DATA */
+		0x000100da /* DENALI_PHY_315_DATA */
+		0x01ff0010 /* DENALI_PHY_316_DATA */
+		0x00000000 /* DENALI_PHY_317_DATA */
+		0x00000000 /* DENALI_PHY_318_DATA */
+		0x00000002 /* DENALI_PHY_319_DATA */
+		0x51313152 /* DENALI_PHY_320_DATA */
+		0x80013130 /* DENALI_PHY_321_DATA */
+		0x02000080 /* DENALI_PHY_322_DATA */
+		0x00100001 /* DENALI_PHY_323_DATA */
+		0x0c064208 /* DENALI_PHY_324_DATA */
+		0x000f0c0f /* DENALI_PHY_325_DATA */
+		0x01000140 /* DENALI_PHY_326_DATA */
+		0x0000000c /* DENALI_PHY_327_DATA */
+		0x00000000 /* DENALI_PHY_328_DATA */
+		0x00000000 /* DENALI_PHY_329_DATA */
+		0x00000000 /* DENALI_PHY_330_DATA */
+		0x00000000 /* DENALI_PHY_331_DATA */
+		0x00000000 /* DENALI_PHY_332_DATA */
+		0x00000000 /* DENALI_PHY_333_DATA */
+		0x00000000 /* DENALI_PHY_334_DATA */
+		0x00000000 /* DENALI_PHY_335_DATA */
+		0x00000000 /* DENALI_PHY_336_DATA */
+		0x00000000 /* DENALI_PHY_337_DATA */
+		0x00000000 /* DENALI_PHY_338_DATA */
+		0x00000000 /* DENALI_PHY_339_DATA */
+		0x00000000 /* DENALI_PHY_340_DATA */
+		0x00000000 /* DENALI_PHY_341_DATA */
+		0x00000000 /* DENALI_PHY_342_DATA */
+		0x00000000 /* DENALI_PHY_343_DATA */
+		0x00000000 /* DENALI_PHY_344_DATA */
+		0x00000000 /* DENALI_PHY_345_DATA */
+		0x00000000 /* DENALI_PHY_346_DATA */
+		0x00000000 /* DENALI_PHY_347_DATA */
+		0x00000000 /* DENALI_PHY_348_DATA */
+		0x00000000 /* DENALI_PHY_349_DATA */
+		0x00000000 /* DENALI_PHY_350_DATA */
+		0x00000000 /* DENALI_PHY_351_DATA */
+		0x00000000 /* DENALI_PHY_352_DATA */
+		0x00000000 /* DENALI_PHY_353_DATA */
+		0x00000000 /* DENALI_PHY_354_DATA */
+		0x00000000 /* DENALI_PHY_355_DATA */
+		0x00000000 /* DENALI_PHY_356_DATA */
+		0x00000000 /* DENALI_PHY_357_DATA */
+		0x00000000 /* DENALI_PHY_358_DATA */
+		0x00000000 /* DENALI_PHY_359_DATA */
+		0x00000000 /* DENALI_PHY_360_DATA */
+		0x00000000 /* DENALI_PHY_361_DATA */
+		0x00000000 /* DENALI_PHY_362_DATA */
+		0x00000000 /* DENALI_PHY_363_DATA */
+		0x00000000 /* DENALI_PHY_364_DATA */
+		0x00000000 /* DENALI_PHY_365_DATA */
+		0x00000000 /* DENALI_PHY_366_DATA */
+		0x00000000 /* DENALI_PHY_367_DATA */
+		0x00000000 /* DENALI_PHY_368_DATA */
+		0x00000000 /* DENALI_PHY_369_DATA */
+		0x00000000 /* DENALI_PHY_370_DATA */
+		0x00000000 /* DENALI_PHY_371_DATA */
+		0x00000000 /* DENALI_PHY_372_DATA */
+		0x00000000 /* DENALI_PHY_373_DATA */
+		0x00000000 /* DENALI_PHY_374_DATA */
+		0x00000000 /* DENALI_PHY_375_DATA */
+		0x00000000 /* DENALI_PHY_376_DATA */
+		0x00000000 /* DENALI_PHY_377_DATA */
+		0x00000000 /* DENALI_PHY_378_DATA */
+		0x00000000 /* DENALI_PHY_379_DATA */
+		0x00000000 /* DENALI_PHY_380_DATA */
+		0x00000000 /* DENALI_PHY_381_DATA */
+		0x00000000 /* DENALI_PHY_382_DATA */
+		0x00000000 /* DENALI_PHY_383_DATA */
+		0x37651240 /* DENALI_PHY_384_DATA */
+		0x0004c008 /* DENALI_PHY_385_DATA */
+		0x000000da /* DENALI_PHY_386_DATA */
+		0x00000000 /* DENALI_PHY_387_DATA */
+		0x00000000 /* DENALI_PHY_388_DATA */
+		0x00010000 /* DENALI_PHY_389_DATA */
+		0x01DDDD90 /* DENALI_PHY_390_DATA */
+		0x01DDDD90 /* DENALI_PHY_391_DATA */
+		0x01030001 /* DENALI_PHY_392_DATA */
+		0x01000000 /* DENALI_PHY_393_DATA */
+		0x00c00000 /* DENALI_PHY_394_DATA */
+		0x00000007 /* DENALI_PHY_395_DATA */
+		0x00000000 /* DENALI_PHY_396_DATA */
+		0x00000000 /* DENALI_PHY_397_DATA */
+		0x04000408 /* DENALI_PHY_398_DATA */
+		0x00000408 /* DENALI_PHY_399_DATA */
+		0x00e4e400 /* DENALI_PHY_400_DATA */
+		0x00000000 /* DENALI_PHY_401_DATA */
+		0x00000000 /* DENALI_PHY_402_DATA */
+		0x00000000 /* DENALI_PHY_403_DATA */
+		0x00000000 /* DENALI_PHY_404_DATA */
+		0x00000000 /* DENALI_PHY_405_DATA */
+		0x00000000 /* DENALI_PHY_406_DATA */
+		0x00000000 /* DENALI_PHY_407_DATA */
+		0x00000000 /* DENALI_PHY_408_DATA */
+		0x00000000 /* DENALI_PHY_409_DATA */
+		0x00000000 /* DENALI_PHY_410_DATA */
+		0x00000000 /* DENALI_PHY_411_DATA */
+		0x00000000 /* DENALI_PHY_412_DATA */
+		0x00000000 /* DENALI_PHY_413_DATA */
+		0x00000000 /* DENALI_PHY_414_DATA */
+		0x00000000 /* DENALI_PHY_415_DATA */
+		0x00000000 /* DENALI_PHY_416_DATA */
+		0x00200000 /* DENALI_PHY_417_DATA */
+		0x00000000 /* DENALI_PHY_418_DATA */
+		0x00000000 /* DENALI_PHY_419_DATA */
+		0x00000000 /* DENALI_PHY_420_DATA */
+		0x00000000 /* DENALI_PHY_421_DATA */
+		0x00000000 /* DENALI_PHY_422_DATA */
+		0x00000000 /* DENALI_PHY_423_DATA */
+		0x02800280 /* DENALI_PHY_424_DATA */
+		0x02800280 /* DENALI_PHY_425_DATA */
+		0x02800280 /* DENALI_PHY_426_DATA */
+		0x02800280 /* DENALI_PHY_427_DATA */
+		0x00000280 /* DENALI_PHY_428_DATA */
+		0x00000000 /* DENALI_PHY_429_DATA */
+		0x00000000 /* DENALI_PHY_430_DATA */
+		0x00000000 /* DENALI_PHY_431_DATA */
+		0x00000000 /* DENALI_PHY_432_DATA */
+		0x00000000 /* DENALI_PHY_433_DATA */
+		0x00800080 /* DENALI_PHY_434_DATA */
+		0x00800080 /* DENALI_PHY_435_DATA */
+		0x00800080 /* DENALI_PHY_436_DATA */
+		0x00800080 /* DENALI_PHY_437_DATA */
+		0x00800080 /* DENALI_PHY_438_DATA */
+		0x00800080 /* DENALI_PHY_439_DATA */
+		0x00800080 /* DENALI_PHY_440_DATA */
+		0x00800080 /* DENALI_PHY_441_DATA */
+		0x00800080 /* DENALI_PHY_442_DATA */
+		0x000100da /* DENALI_PHY_443_DATA */
+		0x01ff0010 /* DENALI_PHY_444_DATA */
+		0x00000000 /* DENALI_PHY_445_DATA */
+		0x00000000 /* DENALI_PHY_446_DATA */
+		0x00000002 /* DENALI_PHY_447_DATA */
+		0x51313152 /* DENALI_PHY_448_DATA */
+		0x80013130 /* DENALI_PHY_449_DATA */
+		0x02000080 /* DENALI_PHY_450_DATA */
+		0x00100001 /* DENALI_PHY_451_DATA */
+		0x0c064208 /* DENALI_PHY_452_DATA */
+		0x000f0c0f /* DENALI_PHY_453_DATA */
+		0x01000140 /* DENALI_PHY_454_DATA */
+		0x0000000c /* DENALI_PHY_455_DATA */
+		0x00000000 /* DENALI_PHY_456_DATA */
+		0x00000000 /* DENALI_PHY_457_DATA */
+		0x00000000 /* DENALI_PHY_458_DATA */
+		0x00000000 /* DENALI_PHY_459_DATA */
+		0x00000000 /* DENALI_PHY_460_DATA */
+		0x00000000 /* DENALI_PHY_461_DATA */
+		0x00000000 /* DENALI_PHY_462_DATA */
+		0x00000000 /* DENALI_PHY_463_DATA */
+		0x00000000 /* DENALI_PHY_464_DATA */
+		0x00000000 /* DENALI_PHY_465_DATA */
+		0x00000000 /* DENALI_PHY_466_DATA */
+		0x00000000 /* DENALI_PHY_467_DATA */
+		0x00000000 /* DENALI_PHY_468_DATA */
+		0x00000000 /* DENALI_PHY_469_DATA */
+		0x00000000 /* DENALI_PHY_470_DATA */
+		0x00000000 /* DENALI_PHY_471_DATA */
+		0x00000000 /* DENALI_PHY_472_DATA */
+		0x00000000 /* DENALI_PHY_473_DATA */
+		0x00000000 /* DENALI_PHY_474_DATA */
+		0x00000000 /* DENALI_PHY_475_DATA */
+		0x00000000 /* DENALI_PHY_476_DATA */
+		0x00000000 /* DENALI_PHY_477_DATA */
+		0x00000000 /* DENALI_PHY_478_DATA */
+		0x00000000 /* DENALI_PHY_479_DATA */
+		0x00000000 /* DENALI_PHY_480_DATA */
+		0x00000000 /* DENALI_PHY_481_DATA */
+		0x00000000 /* DENALI_PHY_482_DATA */
+		0x00000000 /* DENALI_PHY_483_DATA */
+		0x00000000 /* DENALI_PHY_484_DATA */
+		0x00000000 /* DENALI_PHY_485_DATA */
+		0x00000000 /* DENALI_PHY_486_DATA */
+		0x00000000 /* DENALI_PHY_487_DATA */
+		0x00000000 /* DENALI_PHY_488_DATA */
+		0x00000000 /* DENALI_PHY_489_DATA */
+		0x00000000 /* DENALI_PHY_490_DATA */
+		0x00000000 /* DENALI_PHY_491_DATA */
+		0x00000000 /* DENALI_PHY_492_DATA */
+		0x00000000 /* DENALI_PHY_493_DATA */
+		0x00000000 /* DENALI_PHY_494_DATA */
+		0x00000000 /* DENALI_PHY_495_DATA */
+		0x00000000 /* DENALI_PHY_496_DATA */
+		0x00000000 /* DENALI_PHY_497_DATA */
+		0x00000000 /* DENALI_PHY_498_DATA */
+		0x00000000 /* DENALI_PHY_499_DATA */
+		0x00000000 /* DENALI_PHY_500_DATA */
+		0x00000000 /* DENALI_PHY_501_DATA */
+		0x00000000 /* DENALI_PHY_502_DATA */
+		0x00000000 /* DENALI_PHY_503_DATA */
+		0x00000000 /* DENALI_PHY_504_DATA */
+		0x00000000 /* DENALI_PHY_505_DATA */
+		0x00000000 /* DENALI_PHY_506_DATA */
+		0x00000000 /* DENALI_PHY_507_DATA */
+		0x00000000 /* DENALI_PHY_508_DATA */
+		0x00000000 /* DENALI_PHY_509_DATA */
+		0x00000000 /* DENALI_PHY_510_DATA */
+		0x00000000 /* DENALI_PHY_511_DATA */
+		0x34216750 /* DENALI_PHY_512_DATA */
+		0x0004c008 /* DENALI_PHY_513_DATA */
+		0x000000da /* DENALI_PHY_514_DATA */
+		0x00000000 /* DENALI_PHY_515_DATA */
+		0x00000000 /* DENALI_PHY_516_DATA */
+		0x00010000 /* DENALI_PHY_517_DATA */
+		0x01DDDD90 /* DENALI_PHY_518_DATA */
+		0x01DDDD90 /* DENALI_PHY_519_DATA */
+		0x01030001 /* DENALI_PHY_520_DATA */
+		0x01000000 /* DENALI_PHY_521_DATA */
+		0x00c00000 /* DENALI_PHY_522_DATA */
+		0x00000007 /* DENALI_PHY_523_DATA */
+		0x00000000 /* DENALI_PHY_524_DATA */
+		0x00000000 /* DENALI_PHY_525_DATA */
+		0x04000408 /* DENALI_PHY_526_DATA */
+		0x00000408 /* DENALI_PHY_527_DATA */
+		0x00e4e400 /* DENALI_PHY_528_DATA */
+		0x00000000 /* DENALI_PHY_529_DATA */
+		0x00000000 /* DENALI_PHY_530_DATA */
+		0x00000000 /* DENALI_PHY_531_DATA */
+		0x00000000 /* DENALI_PHY_532_DATA */
+		0x00000000 /* DENALI_PHY_533_DATA */
+		0x00000000 /* DENALI_PHY_534_DATA */
+		0x00000000 /* DENALI_PHY_535_DATA */
+		0x00000000 /* DENALI_PHY_536_DATA */
+		0x00000000 /* DENALI_PHY_537_DATA */
+		0x00000000 /* DENALI_PHY_538_DATA */
+		0x00000000 /* DENALI_PHY_539_DATA */
+		0x00000000 /* DENALI_PHY_540_DATA */
+		0x00000000 /* DENALI_PHY_541_DATA */
+		0x00000000 /* DENALI_PHY_542_DATA */
+		0x00000000 /* DENALI_PHY_543_DATA */
+		0x00000000 /* DENALI_PHY_544_DATA */
+		0x00200000 /* DENALI_PHY_545_DATA */
+		0x00000000 /* DENALI_PHY_546_DATA */
+		0x00000000 /* DENALI_PHY_547_DATA */
+		0x00000000 /* DENALI_PHY_548_DATA */
+		0x00000000 /* DENALI_PHY_549_DATA */
+		0x00000000 /* DENALI_PHY_550_DATA */
+		0x00000000 /* DENALI_PHY_551_DATA */
+		0x02800280 /* DENALI_PHY_552_DATA */
+		0x02800280 /* DENALI_PHY_553_DATA */
+		0x02800280 /* DENALI_PHY_554_DATA */
+		0x02800280 /* DENALI_PHY_555_DATA */
+		0x00000280 /* DENALI_PHY_556_DATA */
+		0x00000000 /* DENALI_PHY_557_DATA */
+		0x00000000 /* DENALI_PHY_558_DATA */
+		0x00000000 /* DENALI_PHY_559_DATA */
+		0x00000000 /* DENALI_PHY_560_DATA */
+		0x00000000 /* DENALI_PHY_561_DATA */
+		0x00800080 /* DENALI_PHY_562_DATA */
+		0x00800080 /* DENALI_PHY_563_DATA */
+		0x00800080 /* DENALI_PHY_564_DATA */
+		0x00800080 /* DENALI_PHY_565_DATA */
+		0x00800080 /* DENALI_PHY_566_DATA */
+		0x00800080 /* DENALI_PHY_567_DATA */
+		0x00800080 /* DENALI_PHY_568_DATA */
+		0x00800080 /* DENALI_PHY_569_DATA */
+		0x00800080 /* DENALI_PHY_570_DATA */
+		0x000100da /* DENALI_PHY_571_DATA */
+		0x01ff0010 /* DENALI_PHY_572_DATA */
+		0x00000000 /* DENALI_PHY_573_DATA */
+		0x00000000 /* DENALI_PHY_574_DATA */
+		0x00000002 /* DENALI_PHY_575_DATA */
+		0x51313152 /* DENALI_PHY_576_DATA */
+		0x80013130 /* DENALI_PHY_577_DATA */
+		0x02000080 /* DENALI_PHY_578_DATA */
+		0x00100001 /* DENALI_PHY_579_DATA */
+		0x0c064208 /* DENALI_PHY_580_DATA */
+		0x000f0c0f /* DENALI_PHY_581_DATA */
+		0x01000140 /* DENALI_PHY_582_DATA */
+		0x0000000c /* DENALI_PHY_583_DATA */
+		0x00000000 /* DENALI_PHY_584_DATA */
+		0x00000000 /* DENALI_PHY_585_DATA */
+		0x00000000 /* DENALI_PHY_586_DATA */
+		0x00000000 /* DENALI_PHY_587_DATA */
+		0x00000000 /* DENALI_PHY_588_DATA */
+		0x00000000 /* DENALI_PHY_589_DATA */
+		0x00000000 /* DENALI_PHY_590_DATA */
+		0x00000000 /* DENALI_PHY_591_DATA */
+		0x00000000 /* DENALI_PHY_592_DATA */
+		0x00000000 /* DENALI_PHY_593_DATA */
+		0x00000000 /* DENALI_PHY_594_DATA */
+		0x00000000 /* DENALI_PHY_595_DATA */
+		0x00000000 /* DENALI_PHY_596_DATA */
+		0x00000000 /* DENALI_PHY_597_DATA */
+		0x00000000 /* DENALI_PHY_598_DATA */
+		0x00000000 /* DENALI_PHY_599_DATA */
+		0x00000000 /* DENALI_PHY_600_DATA */
+		0x00000000 /* DENALI_PHY_601_DATA */
+		0x00000000 /* DENALI_PHY_602_DATA */
+		0x00000000 /* DENALI_PHY_603_DATA */
+		0x00000000 /* DENALI_PHY_604_DATA */
+		0x00000000 /* DENALI_PHY_605_DATA */
+		0x00000000 /* DENALI_PHY_606_DATA */
+		0x00000000 /* DENALI_PHY_607_DATA */
+		0x00000000 /* DENALI_PHY_608_DATA */
+		0x00000000 /* DENALI_PHY_609_DATA */
+		0x00000000 /* DENALI_PHY_610_DATA */
+		0x00000000 /* DENALI_PHY_611_DATA */
+		0x00000000 /* DENALI_PHY_612_DATA */
+		0x00000000 /* DENALI_PHY_613_DATA */
+		0x00000000 /* DENALI_PHY_614_DATA */
+		0x00000000 /* DENALI_PHY_615_DATA */
+		0x00000000 /* DENALI_PHY_616_DATA */
+		0x00000000 /* DENALI_PHY_617_DATA */
+		0x00000000 /* DENALI_PHY_618_DATA */
+		0x00000000 /* DENALI_PHY_619_DATA */
+		0x00000000 /* DENALI_PHY_620_DATA */
+		0x00000000 /* DENALI_PHY_621_DATA */
+		0x00000000 /* DENALI_PHY_622_DATA */
+		0x00000000 /* DENALI_PHY_623_DATA */
+		0x00000000 /* DENALI_PHY_624_DATA */
+		0x00000000 /* DENALI_PHY_625_DATA */
+		0x00000000 /* DENALI_PHY_626_DATA */
+		0x00000000 /* DENALI_PHY_627_DATA */
+		0x00000000 /* DENALI_PHY_628_DATA */
+		0x00000000 /* DENALI_PHY_629_DATA */
+		0x00000000 /* DENALI_PHY_630_DATA */
+		0x00000000 /* DENALI_PHY_631_DATA */
+		0x00000000 /* DENALI_PHY_632_DATA */
+		0x00000000 /* DENALI_PHY_633_DATA */
+		0x00000000 /* DENALI_PHY_634_DATA */
+		0x00000000 /* DENALI_PHY_635_DATA */
+		0x00000000 /* DENALI_PHY_636_DATA */
+		0x00000000 /* DENALI_PHY_637_DATA */
+		0x00000000 /* DENALI_PHY_638_DATA */
+		0x00000000 /* DENALI_PHY_639_DATA */
+		0x35176402 /* DENALI_PHY_640_DATA */
+		0x0004c008 /* DENALI_PHY_641_DATA */
+		0x000000da /* DENALI_PHY_642_DATA */
+		0x00000000 /* DENALI_PHY_643_DATA */
+		0x00000000 /* DENALI_PHY_644_DATA */
+		0x00010000 /* DENALI_PHY_645_DATA */
+		0x01DDDD90 /* DENALI_PHY_646_DATA */
+		0x01DDDD90 /* DENALI_PHY_647_DATA */
+		0x01030001 /* DENALI_PHY_648_DATA */
+		0x01000000 /* DENALI_PHY_649_DATA */
+		0x00c00000 /* DENALI_PHY_650_DATA */
+		0x00000007 /* DENALI_PHY_651_DATA */
+		0x00000000 /* DENALI_PHY_652_DATA */
+		0x00000000 /* DENALI_PHY_653_DATA */
+		0x04000408 /* DENALI_PHY_654_DATA */
+		0x00000408 /* DENALI_PHY_655_DATA */
+		0x00e4e400 /* DENALI_PHY_656_DATA */
+		0x00000000 /* DENALI_PHY_657_DATA */
+		0x00000000 /* DENALI_PHY_658_DATA */
+		0x00000000 /* DENALI_PHY_659_DATA */
+		0x00000000 /* DENALI_PHY_660_DATA */
+		0x00000000 /* DENALI_PHY_661_DATA */
+		0x00000000 /* DENALI_PHY_662_DATA */
+		0x00000000 /* DENALI_PHY_663_DATA */
+		0x00000000 /* DENALI_PHY_664_DATA */
+		0x00000000 /* DENALI_PHY_665_DATA */
+		0x00000000 /* DENALI_PHY_666_DATA */
+		0x00000000 /* DENALI_PHY_667_DATA */
+		0x00000000 /* DENALI_PHY_668_DATA */
+		0x00000000 /* DENALI_PHY_669_DATA */
+		0x00000000 /* DENALI_PHY_670_DATA */
+		0x00000000 /* DENALI_PHY_671_DATA */
+		0x00000000 /* DENALI_PHY_672_DATA */
+		0x00200000 /* DENALI_PHY_673_DATA */
+		0x00000000 /* DENALI_PHY_674_DATA */
+		0x00000000 /* DENALI_PHY_675_DATA */
+		0x00000000 /* DENALI_PHY_676_DATA */
+		0x00000000 /* DENALI_PHY_677_DATA */
+		0x00000000 /* DENALI_PHY_678_DATA */
+		0x00000000 /* DENALI_PHY_679_DATA */
+		0x02800280 /* DENALI_PHY_680_DATA */
+		0x02800280 /* DENALI_PHY_681_DATA */
+		0x02800280 /* DENALI_PHY_682_DATA */
+		0x02800280 /* DENALI_PHY_683_DATA */
+		0x00000280 /* DENALI_PHY_684_DATA */
+		0x00000000 /* DENALI_PHY_685_DATA */
+		0x00000000 /* DENALI_PHY_686_DATA */
+		0x00000000 /* DENALI_PHY_687_DATA */
+		0x00000000 /* DENALI_PHY_688_DATA */
+		0x00000000 /* DENALI_PHY_689_DATA */
+		0x00800080 /* DENALI_PHY_690_DATA */
+		0x00800080 /* DENALI_PHY_691_DATA */
+		0x00800080 /* DENALI_PHY_692_DATA */
+		0x00800080 /* DENALI_PHY_693_DATA */
+		0x00800080 /* DENALI_PHY_694_DATA */
+		0x00800080 /* DENALI_PHY_695_DATA */
+		0x00800080 /* DENALI_PHY_696_DATA */
+		0x00800080 /* DENALI_PHY_697_DATA */
+		0x00800080 /* DENALI_PHY_698_DATA */
+		0x000100da /* DENALI_PHY_699_DATA */
+		0x01ff0010 /* DENALI_PHY_700_DATA */
+		0x00000000 /* DENALI_PHY_701_DATA */
+		0x00000000 /* DENALI_PHY_702_DATA */
+		0x00000002 /* DENALI_PHY_703_DATA */
+		0x51313152 /* DENALI_PHY_704_DATA */
+		0x80013130 /* DENALI_PHY_705_DATA */
+		0x02000080 /* DENALI_PHY_706_DATA */
+		0x00100001 /* DENALI_PHY_707_DATA */
+		0x0c064208 /* DENALI_PHY_708_DATA */
+		0x000f0c0f /* DENALI_PHY_709_DATA */
+		0x01000140 /* DENALI_PHY_710_DATA */
+		0x0000000c /* DENALI_PHY_711_DATA */
+		0x00000000 /* DENALI_PHY_712_DATA */
+		0x00000000 /* DENALI_PHY_713_DATA */
+		0x00000000 /* DENALI_PHY_714_DATA */
+		0x00000000 /* DENALI_PHY_715_DATA */
+		0x00000000 /* DENALI_PHY_716_DATA */
+		0x00000000 /* DENALI_PHY_717_DATA */
+		0x00000000 /* DENALI_PHY_718_DATA */
+		0x00000000 /* DENALI_PHY_719_DATA */
+		0x00000000 /* DENALI_PHY_720_DATA */
+		0x00000000 /* DENALI_PHY_721_DATA */
+		0x00000000 /* DENALI_PHY_722_DATA */
+		0x00000000 /* DENALI_PHY_723_DATA */
+		0x00000000 /* DENALI_PHY_724_DATA */
+		0x00000000 /* DENALI_PHY_725_DATA */
+		0x00000000 /* DENALI_PHY_726_DATA */
+		0x00000000 /* DENALI_PHY_727_DATA */
+		0x00000000 /* DENALI_PHY_728_DATA */
+		0x00000000 /* DENALI_PHY_729_DATA */
+		0x00000000 /* DENALI_PHY_730_DATA */
+		0x00000000 /* DENALI_PHY_731_DATA */
+		0x00000000 /* DENALI_PHY_732_DATA */
+		0x00000000 /* DENALI_PHY_733_DATA */
+		0x00000000 /* DENALI_PHY_734_DATA */
+		0x00000000 /* DENALI_PHY_735_DATA */
+		0x00000000 /* DENALI_PHY_736_DATA */
+		0x00000000 /* DENALI_PHY_737_DATA */
+		0x00000000 /* DENALI_PHY_738_DATA */
+		0x00000000 /* DENALI_PHY_739_DATA */
+		0x00000000 /* DENALI_PHY_740_DATA */
+		0x00000000 /* DENALI_PHY_741_DATA */
+		0x00000000 /* DENALI_PHY_742_DATA */
+		0x00000000 /* DENALI_PHY_743_DATA */
+		0x00000000 /* DENALI_PHY_744_DATA */
+		0x00000000 /* DENALI_PHY_745_DATA */
+		0x00000000 /* DENALI_PHY_746_DATA */
+		0x00000000 /* DENALI_PHY_747_DATA */
+		0x00000000 /* DENALI_PHY_748_DATA */
+		0x00000000 /* DENALI_PHY_749_DATA */
+		0x00000000 /* DENALI_PHY_750_DATA */
+		0x00000000 /* DENALI_PHY_751_DATA */
+		0x00000000 /* DENALI_PHY_752_DATA */
+		0x00000000 /* DENALI_PHY_753_DATA */
+		0x00000000 /* DENALI_PHY_754_DATA */
+		0x00000000 /* DENALI_PHY_755_DATA */
+		0x00000000 /* DENALI_PHY_756_DATA */
+		0x00000000 /* DENALI_PHY_757_DATA */
+		0x00000000 /* DENALI_PHY_758_DATA */
+		0x00000000 /* DENALI_PHY_759_DATA */
+		0x00000000 /* DENALI_PHY_760_DATA */
+		0x00000000 /* DENALI_PHY_761_DATA */
+		0x00000000 /* DENALI_PHY_762_DATA */
+		0x00000000 /* DENALI_PHY_763_DATA */
+		0x00000000 /* DENALI_PHY_764_DATA */
+		0x00000000 /* DENALI_PHY_765_DATA */
+		0x00000000 /* DENALI_PHY_766_DATA */
+		0x00000000 /* DENALI_PHY_767_DATA */
+		0x10526347 /* DENALI_PHY_768_DATA */
+		0x0004c008 /* DENALI_PHY_769_DATA */
+		0x000000da /* DENALI_PHY_770_DATA */
+		0x00000000 /* DENALI_PHY_771_DATA */
+		0x00000000 /* DENALI_PHY_772_DATA */
+		0x00010000 /* DENALI_PHY_773_DATA */
+		0x01DDDD90 /* DENALI_PHY_774_DATA */
+		0x01DDDD90 /* DENALI_PHY_775_DATA */
+		0x01030001 /* DENALI_PHY_776_DATA */
+		0x01000000 /* DENALI_PHY_777_DATA */
+		0x00c00000 /* DENALI_PHY_778_DATA */
+		0x00000007 /* DENALI_PHY_779_DATA */
+		0x00000000 /* DENALI_PHY_780_DATA */
+		0x00000000 /* DENALI_PHY_781_DATA */
+		0x04000408 /* DENALI_PHY_782_DATA */
+		0x00000408 /* DENALI_PHY_783_DATA */
+		0x00e4e400 /* DENALI_PHY_784_DATA */
+		0x00000000 /* DENALI_PHY_785_DATA */
+		0x00000000 /* DENALI_PHY_786_DATA */
+		0x00000000 /* DENALI_PHY_787_DATA */
+		0x00000000 /* DENALI_PHY_788_DATA */
+		0x00000000 /* DENALI_PHY_789_DATA */
+		0x00000000 /* DENALI_PHY_790_DATA */
+		0x00000000 /* DENALI_PHY_791_DATA */
+		0x00000000 /* DENALI_PHY_792_DATA */
+		0x00000000 /* DENALI_PHY_793_DATA */
+		0x00000000 /* DENALI_PHY_794_DATA */
+		0x00000000 /* DENALI_PHY_795_DATA */
+		0x00000000 /* DENALI_PHY_796_DATA */
+		0x00000000 /* DENALI_PHY_797_DATA */
+		0x00000000 /* DENALI_PHY_798_DATA */
+		0x00000000 /* DENALI_PHY_799_DATA */
+		0x00000000 /* DENALI_PHY_800_DATA */
+		0x00200000 /* DENALI_PHY_801_DATA */
+		0x00000000 /* DENALI_PHY_802_DATA */
+		0x00000000 /* DENALI_PHY_803_DATA */
+		0x00000000 /* DENALI_PHY_804_DATA */
+		0x00000000 /* DENALI_PHY_805_DATA */
+		0x00000000 /* DENALI_PHY_806_DATA */
+		0x00000000 /* DENALI_PHY_807_DATA */
+		0x02800280 /* DENALI_PHY_808_DATA */
+		0x02800280 /* DENALI_PHY_809_DATA */
+		0x02800280 /* DENALI_PHY_810_DATA */
+		0x02800280 /* DENALI_PHY_811_DATA */
+		0x00000280 /* DENALI_PHY_812_DATA */
+		0x00000000 /* DENALI_PHY_813_DATA */
+		0x00000000 /* DENALI_PHY_814_DATA */
+		0x00000000 /* DENALI_PHY_815_DATA */
+		0x00000000 /* DENALI_PHY_816_DATA */
+		0x00000000 /* DENALI_PHY_817_DATA */
+		0x00800080 /* DENALI_PHY_818_DATA */
+		0x00800080 /* DENALI_PHY_819_DATA */
+		0x00800080 /* DENALI_PHY_820_DATA */
+		0x00800080 /* DENALI_PHY_821_DATA */
+		0x00800080 /* DENALI_PHY_822_DATA */
+		0x00800080 /* DENALI_PHY_823_DATA */
+		0x00800080 /* DENALI_PHY_824_DATA */
+		0x00800080 /* DENALI_PHY_825_DATA */
+		0x00800080 /* DENALI_PHY_826_DATA */
+		0x000100da /* DENALI_PHY_827_DATA */
+		0x01ff0010 /* DENALI_PHY_828_DATA */
+		0x00000000 /* DENALI_PHY_829_DATA */
+		0x00000000 /* DENALI_PHY_830_DATA */
+		0x00000002 /* DENALI_PHY_831_DATA */
+		0x51313152 /* DENALI_PHY_832_DATA */
+		0x80013130 /* DENALI_PHY_833_DATA */
+		0x02000080 /* DENALI_PHY_834_DATA */
+		0x00100001 /* DENALI_PHY_835_DATA */
+		0x0c064208 /* DENALI_PHY_836_DATA */
+		0x000f0c0f /* DENALI_PHY_837_DATA */
+		0x01000140 /* DENALI_PHY_838_DATA */
+		0x0000000c /* DENALI_PHY_839_DATA */
+		0x00000000 /* DENALI_PHY_840_DATA */
+		0x00000000 /* DENALI_PHY_841_DATA */
+		0x00000000 /* DENALI_PHY_842_DATA */
+		0x00000000 /* DENALI_PHY_843_DATA */
+		0x00000000 /* DENALI_PHY_844_DATA */
+		0x00000000 /* DENALI_PHY_845_DATA */
+		0x00000000 /* DENALI_PHY_846_DATA */
+		0x00000000 /* DENALI_PHY_847_DATA */
+		0x00000000 /* DENALI_PHY_848_DATA */
+		0x00000000 /* DENALI_PHY_849_DATA */
+		0x00000000 /* DENALI_PHY_850_DATA */
+		0x00000000 /* DENALI_PHY_851_DATA */
+		0x00000000 /* DENALI_PHY_852_DATA */
+		0x00000000 /* DENALI_PHY_853_DATA */
+		0x00000000 /* DENALI_PHY_854_DATA */
+		0x00000000 /* DENALI_PHY_855_DATA */
+		0x00000000 /* DENALI_PHY_856_DATA */
+		0x00000000 /* DENALI_PHY_857_DATA */
+		0x00000000 /* DENALI_PHY_858_DATA */
+		0x00000000 /* DENALI_PHY_859_DATA */
+		0x00000000 /* DENALI_PHY_860_DATA */
+		0x00000000 /* DENALI_PHY_861_DATA */
+		0x00000000 /* DENALI_PHY_862_DATA */
+		0x00000000 /* DENALI_PHY_863_DATA */
+		0x00000000 /* DENALI_PHY_864_DATA */
+		0x00000000 /* DENALI_PHY_865_DATA */
+		0x00000000 /* DENALI_PHY_866_DATA */
+		0x00000000 /* DENALI_PHY_867_DATA */
+		0x00000000 /* DENALI_PHY_868_DATA */
+		0x00000000 /* DENALI_PHY_869_DATA */
+		0x00000000 /* DENALI_PHY_870_DATA */
+		0x00000000 /* DENALI_PHY_871_DATA */
+		0x00000000 /* DENALI_PHY_872_DATA */
+		0x00000000 /* DENALI_PHY_873_DATA */
+		0x00000000 /* DENALI_PHY_874_DATA */
+		0x00000000 /* DENALI_PHY_875_DATA */
+		0x00000000 /* DENALI_PHY_876_DATA */
+		0x00000000 /* DENALI_PHY_877_DATA */
+		0x00000000 /* DENALI_PHY_878_DATA */
+		0x00000000 /* DENALI_PHY_879_DATA */
+		0x00000000 /* DENALI_PHY_880_DATA */
+		0x00000000 /* DENALI_PHY_881_DATA */
+		0x00000000 /* DENALI_PHY_882_DATA */
+		0x00000000 /* DENALI_PHY_883_DATA */
+		0x00000000 /* DENALI_PHY_884_DATA */
+		0x00000000 /* DENALI_PHY_885_DATA */
+		0x00000000 /* DENALI_PHY_886_DATA */
+		0x00000000 /* DENALI_PHY_887_DATA */
+		0x00000000 /* DENALI_PHY_888_DATA */
+		0x00000000 /* DENALI_PHY_889_DATA */
+		0x00000000 /* DENALI_PHY_890_DATA */
+		0x00000000 /* DENALI_PHY_891_DATA */
+		0x00000000 /* DENALI_PHY_892_DATA */
+		0x00000000 /* DENALI_PHY_893_DATA */
+		0x00000000 /* DENALI_PHY_894_DATA */
+		0x00000000 /* DENALI_PHY_895_DATA */
+		0x41753260 /* DENALI_PHY_896_DATA */
+		0x0004c008 /* DENALI_PHY_897_DATA */
+		0x000000da /* DENALI_PHY_898_DATA */
+		0x00000000 /* DENALI_PHY_899_DATA */
+		0x00000000 /* DENALI_PHY_900_DATA */
+		0x00010000 /* DENALI_PHY_901_DATA */
+		0x01DDDD90 /* DENALI_PHY_902_DATA */
+		0x01DDDD90 /* DENALI_PHY_903_DATA */
+		0x01030001 /* DENALI_PHY_904_DATA */
+		0x01000000 /* DENALI_PHY_905_DATA */
+		0x00c00000 /* DENALI_PHY_906_DATA */
+		0x00000007 /* DENALI_PHY_907_DATA */
+		0x00000000 /* DENALI_PHY_908_DATA */
+		0x00000000 /* DENALI_PHY_909_DATA */
+		0x04000408 /* DENALI_PHY_910_DATA */
+		0x00000408 /* DENALI_PHY_911_DATA */
+		0x00e4e400 /* DENALI_PHY_912_DATA */
+		0x00000000 /* DENALI_PHY_913_DATA */
+		0x00000000 /* DENALI_PHY_914_DATA */
+		0x00000000 /* DENALI_PHY_915_DATA */
+		0x00000000 /* DENALI_PHY_916_DATA */
+		0x00000000 /* DENALI_PHY_917_DATA */
+		0x00000000 /* DENALI_PHY_918_DATA */
+		0x00000000 /* DENALI_PHY_919_DATA */
+		0x00000000 /* DENALI_PHY_920_DATA */
+		0x00000000 /* DENALI_PHY_921_DATA */
+		0x00000000 /* DENALI_PHY_922_DATA */
+		0x00000000 /* DENALI_PHY_923_DATA */
+		0x00000000 /* DENALI_PHY_924_DATA */
+		0x00000000 /* DENALI_PHY_925_DATA */
+		0x00000000 /* DENALI_PHY_926_DATA */
+		0x00000000 /* DENALI_PHY_927_DATA */
+		0x00000000 /* DENALI_PHY_928_DATA */
+		0x00200000 /* DENALI_PHY_929_DATA */
+		0x00000000 /* DENALI_PHY_930_DATA */
+		0x00000000 /* DENALI_PHY_931_DATA */
+		0x00000000 /* DENALI_PHY_932_DATA */
+		0x00000000 /* DENALI_PHY_933_DATA */
+		0x00000000 /* DENALI_PHY_934_DATA */
+		0x00000000 /* DENALI_PHY_935_DATA */
+		0x02800280 /* DENALI_PHY_936_DATA */
+		0x02800280 /* DENALI_PHY_937_DATA */
+		0x02800280 /* DENALI_PHY_938_DATA */
+		0x02800280 /* DENALI_PHY_939_DATA */
+		0x00000280 /* DENALI_PHY_940_DATA */
+		0x00000000 /* DENALI_PHY_941_DATA */
+		0x00000000 /* DENALI_PHY_942_DATA */
+		0x00000000 /* DENALI_PHY_943_DATA */
+		0x00000000 /* DENALI_PHY_944_DATA */
+		0x00000000 /* DENALI_PHY_945_DATA */
+		0x00800080 /* DENALI_PHY_946_DATA */
+		0x00800080 /* DENALI_PHY_947_DATA */
+		0x00800080 /* DENALI_PHY_948_DATA */
+		0x00800080 /* DENALI_PHY_949_DATA */
+		0x00800080 /* DENALI_PHY_950_DATA */
+		0x00800080 /* DENALI_PHY_951_DATA */
+		0x00800080 /* DENALI_PHY_952_DATA */
+		0x00800080 /* DENALI_PHY_953_DATA */
+		0x00800080 /* DENALI_PHY_954_DATA */
+		0x000100da /* DENALI_PHY_955_DATA */
+		0x01ff0010 /* DENALI_PHY_956_DATA */
+		0x00000000 /* DENALI_PHY_957_DATA */
+		0x00000000 /* DENALI_PHY_958_DATA */
+		0x00000002 /* DENALI_PHY_959_DATA */
+		0x51313152 /* DENALI_PHY_960_DATA */
+		0x80013130 /* DENALI_PHY_961_DATA */
+		0x02000080 /* DENALI_PHY_962_DATA */
+		0x00100001 /* DENALI_PHY_963_DATA */
+		0x0c064208 /* DENALI_PHY_964_DATA */
+		0x000f0c0f /* DENALI_PHY_965_DATA */
+		0x01000140 /* DENALI_PHY_966_DATA */
+		0x0000000c /* DENALI_PHY_967_DATA */
+		0x00000000 /* DENALI_PHY_968_DATA */
+		0x00000000 /* DENALI_PHY_969_DATA */
+		0x00000000 /* DENALI_PHY_970_DATA */
+		0x00000000 /* DENALI_PHY_971_DATA */
+		0x00000000 /* DENALI_PHY_972_DATA */
+		0x00000000 /* DENALI_PHY_973_DATA */
+		0x00000000 /* DENALI_PHY_974_DATA */
+		0x00000000 /* DENALI_PHY_975_DATA */
+		0x00000000 /* DENALI_PHY_976_DATA */
+		0x00000000 /* DENALI_PHY_977_DATA */
+		0x00000000 /* DENALI_PHY_978_DATA */
+		0x00000000 /* DENALI_PHY_979_DATA */
+		0x00000000 /* DENALI_PHY_980_DATA */
+		0x00000000 /* DENALI_PHY_981_DATA */
+		0x00000000 /* DENALI_PHY_982_DATA */
+		0x00000000 /* DENALI_PHY_983_DATA */
+		0x00000000 /* DENALI_PHY_984_DATA */
+		0x00000000 /* DENALI_PHY_985_DATA */
+		0x00000000 /* DENALI_PHY_986_DATA */
+		0x00000000 /* DENALI_PHY_987_DATA */
+		0x00000000 /* DENALI_PHY_988_DATA */
+		0x00000000 /* DENALI_PHY_989_DATA */
+		0x00000000 /* DENALI_PHY_990_DATA */
+		0x00000000 /* DENALI_PHY_991_DATA */
+		0x00000000 /* DENALI_PHY_992_DATA */
+		0x00000000 /* DENALI_PHY_993_DATA */
+		0x00000000 /* DENALI_PHY_994_DATA */
+		0x00000000 /* DENALI_PHY_995_DATA */
+		0x00000000 /* DENALI_PHY_996_DATA */
+		0x00000000 /* DENALI_PHY_997_DATA */
+		0x00000000 /* DENALI_PHY_998_DATA */
+		0x00000000 /* DENALI_PHY_999_DATA */
+		0x00000000 /* DENALI_PHY_1000_DATA */
+		0x00000000 /* DENALI_PHY_1001_DATA */
+		0x00000000 /* DENALI_PHY_1002_DATA */
+		0x00000000 /* DENALI_PHY_1003_DATA */
+		0x00000000 /* DENALI_PHY_1004_DATA */
+		0x00000000 /* DENALI_PHY_1005_DATA */
+		0x00000000 /* DENALI_PHY_1006_DATA */
+		0x00000000 /* DENALI_PHY_1007_DATA */
+		0x00000000 /* DENALI_PHY_1008_DATA */
+		0x00000000 /* DENALI_PHY_1009_DATA */
+		0x00000000 /* DENALI_PHY_1010_DATA */
+		0x00000000 /* DENALI_PHY_1011_DATA */
+		0x00000000 /* DENALI_PHY_1012_DATA */
+		0x00000000 /* DENALI_PHY_1013_DATA */
+		0x00000000 /* DENALI_PHY_1014_DATA */
+		0x00000000 /* DENALI_PHY_1015_DATA */
+		0x00000000 /* DENALI_PHY_1016_DATA */
+		0x00000000 /* DENALI_PHY_1017_DATA */
+		0x00000000 /* DENALI_PHY_1018_DATA */
+		0x00000000 /* DENALI_PHY_1019_DATA */
+		0x00000000 /* DENALI_PHY_1020_DATA */
+		0x00000000 /* DENALI_PHY_1021_DATA */
+		0x00000000 /* DENALI_PHY_1022_DATA */
+		0x00000000 /* DENALI_PHY_1023_DATA */
+		0x76543210 /* DENALI_PHY_1024_DATA */
+		0x0004c008 /* DENALI_PHY_1025_DATA */
+		0x000000da /* DENALI_PHY_1026_DATA */
+		0x00000000 /* DENALI_PHY_1027_DATA */
+		0x00000000 /* DENALI_PHY_1028_DATA */
+		0x00010000 /* DENALI_PHY_1029_DATA */
+		0x01665555 /* DENALI_PHY_1030_DATA */
+		0x01665555 /* DENALI_PHY_1031_DATA */
+		0x01030001 /* DENALI_PHY_1032_DATA */
+		0x01000000 /* DENALI_PHY_1033_DATA */
+		0x00c00000 /* DENALI_PHY_1034_DATA */
+		0x00000007 /* DENALI_PHY_1035_DATA */
+		0x00000000 /* DENALI_PHY_1036_DATA */
+		0x00000000 /* DENALI_PHY_1037_DATA */
+		0x04000408 /* DENALI_PHY_1038_DATA */
+		0x00000408 /* DENALI_PHY_1039_DATA */
+		0x00e4e400 /* DENALI_PHY_1040_DATA */
+		0x00000000 /* DENALI_PHY_1041_DATA */
+		0x00000000 /* DENALI_PHY_1042_DATA */
+		0x00000000 /* DENALI_PHY_1043_DATA */
+		0x00000000 /* DENALI_PHY_1044_DATA */
+		0x00000000 /* DENALI_PHY_1045_DATA */
+		0x00000000 /* DENALI_PHY_1046_DATA */
+		0x00000000 /* DENALI_PHY_1047_DATA */
+		0x00000000 /* DENALI_PHY_1048_DATA */
+		0x00000000 /* DENALI_PHY_1049_DATA */
+		0x00000000 /* DENALI_PHY_1050_DATA */
+		0x00000000 /* DENALI_PHY_1051_DATA */
+		0x00000000 /* DENALI_PHY_1052_DATA */
+		0x00000000 /* DENALI_PHY_1053_DATA */
+		0x00000000 /* DENALI_PHY_1054_DATA */
+		0x00000000 /* DENALI_PHY_1055_DATA */
+		0x00000000 /* DENALI_PHY_1056_DATA */
+		0x00200000 /* DENALI_PHY_1057_DATA */
+		0x00000000 /* DENALI_PHY_1058_DATA */
+		0x00000000 /* DENALI_PHY_1059_DATA */
+		0x00000000 /* DENALI_PHY_1060_DATA */
+		0x00000000 /* DENALI_PHY_1061_DATA */
+		0x00000000 /* DENALI_PHY_1062_DATA */
+		0x00000000 /* DENALI_PHY_1063_DATA */
+		0x02800280 /* DENALI_PHY_1064_DATA */
+		0x02800280 /* DENALI_PHY_1065_DATA */
+		0x02800280 /* DENALI_PHY_1066_DATA */
+		0x02800280 /* DENALI_PHY_1067_DATA */
+		0x00000280 /* DENALI_PHY_1068_DATA */
+		0x00000000 /* DENALI_PHY_1069_DATA */
+		0x00000000 /* DENALI_PHY_1070_DATA */
+		0x00000000 /* DENALI_PHY_1071_DATA */
+		0x00000000 /* DENALI_PHY_1072_DATA */
+		0x00000000 /* DENALI_PHY_1073_DATA */
+		0x00800080 /* DENALI_PHY_1074_DATA */
+		0x00800080 /* DENALI_PHY_1075_DATA */
+		0x00800080 /* DENALI_PHY_1076_DATA */
+		0x00800080 /* DENALI_PHY_1077_DATA */
+		0x00800080 /* DENALI_PHY_1078_DATA */
+		0x00800080 /* DENALI_PHY_1079_DATA */
+		0x00800080 /* DENALI_PHY_1080_DATA */
+		0x00800080 /* DENALI_PHY_1081_DATA */
+		0x00800080 /* DENALI_PHY_1082_DATA */
+		0x000100da /* DENALI_PHY_1083_DATA */
+		0x01ff0010 /* DENALI_PHY_1084_DATA */
+		0x00000000 /* DENALI_PHY_1085_DATA */
+		0x00000000 /* DENALI_PHY_1086_DATA */
+		0x00000002 /* DENALI_PHY_1087_DATA */
+		0x51313152 /* DENALI_PHY_1088_DATA */
+		0x80013130 /* DENALI_PHY_1089_DATA */
+		0x02000080 /* DENALI_PHY_1090_DATA */
+		0x00100001 /* DENALI_PHY_1091_DATA */
+		0x0c064208 /* DENALI_PHY_1092_DATA */
+		0x000f0c0f /* DENALI_PHY_1093_DATA */
+		0x01000140 /* DENALI_PHY_1094_DATA */
+		0x0000000c /* DENALI_PHY_1095_DATA */
+		0x00000000 /* DENALI_PHY_1096_DATA */
+		0x00000000 /* DENALI_PHY_1097_DATA */
+		0x00000000 /* DENALI_PHY_1098_DATA */
+		0x00000000 /* DENALI_PHY_1099_DATA */
+		0x00000000 /* DENALI_PHY_1100_DATA */
+		0x00000000 /* DENALI_PHY_1101_DATA */
+		0x00000000 /* DENALI_PHY_1102_DATA */
+		0x00000000 /* DENALI_PHY_1103_DATA */
+		0x00000000 /* DENALI_PHY_1104_DATA */
+		0x00000000 /* DENALI_PHY_1105_DATA */
+		0x00000000 /* DENALI_PHY_1106_DATA */
+		0x00000000 /* DENALI_PHY_1107_DATA */
+		0x00000000 /* DENALI_PHY_1108_DATA */
+		0x00000000 /* DENALI_PHY_1109_DATA */
+		0x00000000 /* DENALI_PHY_1110_DATA */
+		0x00000000 /* DENALI_PHY_1111_DATA */
+		0x00000000 /* DENALI_PHY_1112_DATA */
+		0x00000000 /* DENALI_PHY_1113_DATA */
+		0x00000000 /* DENALI_PHY_1114_DATA */
+		0x00000000 /* DENALI_PHY_1115_DATA */
+		0x00000000 /* DENALI_PHY_1116_DATA */
+		0x00000000 /* DENALI_PHY_1117_DATA */
+		0x00000000 /* DENALI_PHY_1118_DATA */
+		0x00000000 /* DENALI_PHY_1119_DATA */
+		0x00000000 /* DENALI_PHY_1120_DATA */
+		0x00000000 /* DENALI_PHY_1121_DATA */
+		0x00000000 /* DENALI_PHY_1122_DATA */
+		0x00000000 /* DENALI_PHY_1123_DATA */
+		0x00000000 /* DENALI_PHY_1124_DATA */
+		0x00000000 /* DENALI_PHY_1125_DATA */
+		0x00000000 /* DENALI_PHY_1126_DATA */
+		0x00000000 /* DENALI_PHY_1127_DATA */
+		0x00000000 /* DENALI_PHY_1128_DATA */
+		0x00000000 /* DENALI_PHY_1129_DATA */
+		0x00000000 /* DENALI_PHY_1130_DATA */
+		0x00000000 /* DENALI_PHY_1131_DATA */
+		0x00000000 /* DENALI_PHY_1132_DATA */
+		0x00000000 /* DENALI_PHY_1133_DATA */
+		0x00000000 /* DENALI_PHY_1134_DATA */
+		0x00000000 /* DENALI_PHY_1135_DATA */
+		0x00000000 /* DENALI_PHY_1136_DATA */
+		0x00000000 /* DENALI_PHY_1137_DATA */
+		0x00000000 /* DENALI_PHY_1138_DATA */
+		0x00000000 /* DENALI_PHY_1139_DATA */
+		0x00000000 /* DENALI_PHY_1140_DATA */
+		0x00000000 /* DENALI_PHY_1141_DATA */
+		0x00000000 /* DENALI_PHY_1142_DATA */
+		0x00000000 /* DENALI_PHY_1143_DATA */
+		0x00000000 /* DENALI_PHY_1144_DATA */
+		0x00000000 /* DENALI_PHY_1145_DATA */
+		0x00000000 /* DENALI_PHY_1146_DATA */
+		0x00000000 /* DENALI_PHY_1147_DATA */
+		0x00000000 /* DENALI_PHY_1148_DATA */
+		0x00000000 /* DENALI_PHY_1149_DATA */
+		0x00000000 /* DENALI_PHY_1150_DATA */
+		0x00000000 /* DENALI_PHY_1151_DATA */
+		0x00000000 /* DENALI_PHY_1152_DATA */
+		0x00000000 /* DENALI_PHY_1153_DATA */
+		0x00050000 /* DENALI_PHY_1154_DATA */
+		0x00000000 /* DENALI_PHY_1155_DATA */
+		0x00000000 /* DENALI_PHY_1156_DATA */
+		0x00000000 /* DENALI_PHY_1157_DATA */
+		0x00000100 /* DENALI_PHY_1158_DATA */
+		0x00000000 /* DENALI_PHY_1159_DATA */
+		0x00000000 /* DENALI_PHY_1160_DATA */
+		0x00506401 /* DENALI_PHY_1161_DATA */
+		0x01221102 /* DENALI_PHY_1162_DATA */
+		0x00000122 /* DENALI_PHY_1163_DATA */
+		0x00000000 /* DENALI_PHY_1164_DATA */
+		0x000B1F00 /* DENALI_PHY_1165_DATA */
+		0x0B1F0B1F /* DENALI_PHY_1166_DATA */
+		0x0B1F0B1F /* DENALI_PHY_1167_DATA */
+		0x0B1F0B1F /* DENALI_PHY_1168_DATA */
+		0x0B1F0B1F /* DENALI_PHY_1169_DATA */
+		0x00000B00 /* DENALI_PHY_1170_DATA */
+		0x42080010 /* DENALI_PHY_1171_DATA */
+		0x01000100 /* DENALI_PHY_1172_DATA */
+		0x01000100 /* DENALI_PHY_1173_DATA */
+		0x01000100 /* DENALI_PHY_1174_DATA */
+		0x01000100 /* DENALI_PHY_1175_DATA */
+		0x00000000 /* DENALI_PHY_1176_DATA */
+		0x00000000 /* DENALI_PHY_1177_DATA */
+		0x00000000 /* DENALI_PHY_1178_DATA */
+		0x00000000 /* DENALI_PHY_1179_DATA */
+		0x00000000 /* DENALI_PHY_1180_DATA */
+		0x00000803 /* DENALI_PHY_1181_DATA */
+		0x223FFF00 /* DENALI_PHY_1182_DATA */
+		0x000008FF /* DENALI_PHY_1183_DATA */
+		0x0000057F /* DENALI_PHY_1184_DATA */
+		0x0000057F /* DENALI_PHY_1185_DATA */
+		0x00037FFF /* DENALI_PHY_1186_DATA */
+		0x00037FFF /* DENALI_PHY_1187_DATA */
+		0x00004410 /* DENALI_PHY_1188_DATA */
+		0x00004410 /* DENALI_PHY_1189_DATA */
+		0x00004410 /* DENALI_PHY_1190_DATA */
+		0x00004410 /* DENALI_PHY_1191_DATA */
+		0x00004410 /* DENALI_PHY_1192_DATA */
+		0x00000111 /* DENALI_PHY_1193_DATA */
+		0x00000111 /* DENALI_PHY_1194_DATA */
+		0x00000000 /* DENALI_PHY_1195_DATA */
+		0x00000000 /* DENALI_PHY_1196_DATA */
+		0x00000000 /* DENALI_PHY_1197_DATA */
+		0x04000000 /* DENALI_PHY_1198_DATA */
+		0x00000000 /* DENALI_PHY_1199_DATA */
+		0x00000000 /* DENALI_PHY_1200_DATA */
+		0x00000108 /* DENALI_PHY_1201_DATA */
+		0x00000000 /* DENALI_PHY_1202_DATA */
+		0x00000000 /* DENALI_PHY_1203_DATA */
+		0x00000000 /* DENALI_PHY_1204_DATA */
+		0x00000001 /* DENALI_PHY_1205_DATA */
+		0x00000000 /* DENALI_PHY_1206_DATA */
+		0x00000000 /* DENALI_PHY_1207_DATA */
+		0x00000000 /* DENALI_PHY_1208_DATA */
+		0x00000000 /* DENALI_PHY_1209_DATA */
+		0x00000000 /* DENALI_PHY_1210_DATA */
+		0x00000000 /* DENALI_PHY_1211_DATA */
+		0x00020100 /* DENALI_PHY_1212_DATA */
+		0x00000000 /* DENALI_PHY_1213_DATA */
+		0x00000000 /* DENALI_PHY_1214_DATA */
+	>;
+};
diff --git a/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi b/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
new file mode 100644
index 0000000..3dcd2b4
--- /dev/null
+++ b/arch/riscv/dts/hifive-unmatched-a00-u-boot.dtsi
@@ -0,0 +1,40 @@ 
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2020-2021 SiFive, Inc
+ */
+
+#include "fu740-c000-u-boot.dtsi"
+#include "fu740-hifive-unmatched-a00-ddr.dtsi"
+
+/ {
+	aliases {
+		spi0 = &spi0;
+	};
+
+	memory@80000000 {
+		u-boot,dm-spl;
+	};
+
+	hfclk {
+		u-boot,dm-spl;
+	};
+
+	rtcclk {
+		u-boot,dm-spl;
+	};
+
+};
+
+&clint {
+	clocks = <&rtcclk>;
+};
+
+&spi0 {
+	mmc@0 {
+		u-boot,dm-spl;
+	};
+};
+
+&gpio {
+	u-boot,dm-spl;
+};
diff --git a/arch/riscv/dts/hifive-unmatched-a00.dts b/arch/riscv/dts/hifive-unmatched-a00.dts
new file mode 100644
index 0000000..92410b4
--- /dev/null
+++ b/arch/riscv/dts/hifive-unmatched-a00.dts
@@ -0,0 +1,263 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/* Copyright (c) 2019-2021 SiFive, Inc */
+
+#include "fu740-c000.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/* Clock frequency (in Hz) of the PCB crystal for rtcclk */
+#define RTCCLK_FREQ		1000000
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	model = "SiFive HiFive Unmatched A00";
+	compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000",
+		     "sifive,fu740";
+
+	chosen {
+		stdout-path = "serial0";
+	};
+
+	cpus {
+		timebase-frequency = <RTCCLK_FREQ>;
+	};
+
+	memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x4 0x00000000>;
+	};
+
+	soc {
+	};
+
+	hfclk: hfclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <26000000>;
+		clock-output-names = "hfclk";
+	};
+
+	rtcclk: rtcclk {
+		#clock-cells = <0>;
+		compatible = "fixed-clock";
+		clock-frequency = <RTCCLK_FREQ>;
+		clock-output-names = "rtcclk";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+
+	temperature-sensor@4c {
+		compatible = "ti,tmp451";
+		reg = <0x4c>;
+		interrupt-parent = <&gpio>;
+		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+	};
+
+	pmic@58 {
+		compatible = "dlg,da9063";
+		reg = <0x58>;
+		interrupt-parent = <&gpio>;
+		interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
+		interrupt-controller;
+
+		regulators {
+			vdd_bcore1: bcore1 {
+				regulator-min-microvolt = <1050000>;
+				regulator-max-microvolt = <1050000>;
+				regulator-min-microamp = <5000000>;
+				regulator-max-microamp = <5000000>;
+				regulator-always-on;
+			};
+
+			vdd_bcore2: bcore2 {
+				regulator-min-microvolt = <1050000>;
+				regulator-max-microvolt = <1050000>;
+				regulator-min-microamp = <5000000>;
+				regulator-max-microamp = <5000000>;
+				regulator-always-on;
+			};
+
+			vdd_bpro: bpro {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-min-microamp = <2500000>;
+				regulator-max-microamp = <2500000>;
+				regulator-always-on;
+			};
+
+			vdd_bperi: bperi {
+				regulator-min-microvolt = <1050000>;
+				regulator-max-microvolt = <1050000>;
+				regulator-min-microamp = <1500000>;
+				regulator-max-microamp = <1500000>;
+				regulator-always-on;
+			};
+
+			vdd_bmem: bmem {
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-min-microamp = <3000000>;
+				regulator-max-microamp = <3000000>;
+				regulator-always-on;
+			};
+
+			vdd_bio: bio {
+				regulator-min-microvolt = <1200000>;
+				regulator-max-microvolt = <1200000>;
+				regulator-min-microamp = <3000000>;
+				regulator-max-microamp = <3000000>;
+				regulator-always-on;
+			};
+
+			vdd_ldo1: ldo1 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-min-microamp = <100000>;
+				regulator-max-microamp = <100000>;
+				regulator-always-on;
+			};
+
+			vdd_ldo2: ldo2 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-min-microamp = <200000>;
+				regulator-max-microamp = <200000>;
+				regulator-always-on;
+			};
+
+			vdd_ldo3: ldo3 {
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microamp = <200000>;
+				regulator-max-microamp = <200000>;
+				regulator-always-on;
+			};
+
+			vdd_ldo4: ldo4 {
+				regulator-min-microvolt = <2500000>;
+				regulator-max-microvolt = <2500000>;
+				regulator-min-microamp = <200000>;
+				regulator-max-microamp = <200000>;
+				regulator-always-on;
+			};
+
+			vdd_ldo5: ldo5 {
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microamp = <100000>;
+				regulator-max-microamp = <100000>;
+				regulator-always-on;
+			};
+
+			vdd_ldo6: ldo6 {
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+				regulator-min-microamp = <200000>;
+				regulator-max-microamp = <200000>;
+				regulator-always-on;
+			};
+
+			vdd_ldo7: ldo7 {
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microamp = <200000>;
+				regulator-max-microamp = <200000>;
+				regulator-always-on;
+			};
+
+			vdd_ldo8: ldo8 {
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-min-microamp = <200000>;
+				regulator-max-microamp = <200000>;
+				regulator-always-on;
+			};
+
+			vdd_ld09: ldo9 {
+				regulator-min-microvolt = <1050000>;
+				regulator-max-microvolt = <1050000>;
+				regulator-min-microamp = <200000>;
+				regulator-max-microamp = <200000>;
+			};
+
+			vdd_ldo10: ldo10 {
+				regulator-min-microvolt = <1000000>;
+				regulator-max-microvolt = <1000000>;
+				regulator-min-microamp = <300000>;
+				regulator-max-microamp = <300000>;
+			};
+
+			vdd_ldo11: ldo11 {
+				regulator-min-microvolt = <2500000>;
+				regulator-max-microvolt = <2500000>;
+				regulator-min-microamp = <300000>;
+				regulator-max-microamp = <300000>;
+				regulator-always-on;
+			};
+		};
+	};
+
+	temperature-sensor@4c {
+		compatible = "ti,tmp451";
+		reg = <0x4c>;
+		interrupt-parent = <&gpio>;
+		interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+		vcc-supply = <&vdd_bpro>;
+		#thermal-sensor-cells = <1>;
+	};
+
+};
+
+&qspi0 {
+	status = "okay";
+	flash@0 {
+		compatible = "issi,is25wp256", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+	};
+};
+
+&spi0 {
+	status = "okay";
+	mmc@0 {
+		compatible = "mmc-spi-slot";
+		reg = <0>;
+		spi-max-frequency = <20000000>;
+		voltage-ranges = <3300 3300>;
+		disable-wp;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	phy-mode = "gmii";
+	phy-handle = <&phy0>;
+	phy0: ethernet-phy@0 {
+		reg = <0>;
+	};
+};
+
+&pwm0 {
+	status = "okay";
+};
+
+&pwm1 {
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig
index 64fdbd4..e70d1e5 100644
--- a/board/sifive/fu540/Kconfig
+++ b/board/sifive/fu540/Kconfig
@@ -47,6 +47,5 @@  config BOARD_SPECIFIC_OPTIONS # dummy
 	imply SPI_FLASH_ISSI
 	imply SYSRESET
 	imply SYSRESET_GPIO
-	imply CMD_I2C
 
 endif
diff --git a/board/sifive/fu540/fu540.c b/board/sifive/fu540/fu540.c
index a4e7822..54e5a4c 100644
--- a/board/sifive/fu540/fu540.c
+++ b/board/sifive/fu540/fu540.c
@@ -58,7 +58,7 @@  static u32 fu540_read_serialnum(void)
 
 	/* init OTP */
 	ret = uclass_get_device_by_driver(UCLASS_MISC,
-					  DM_DRIVER_GET(sifive_otp), &dev);
+					  DM_GET_DRIVER(sifive_otp), &dev);
 
 	if (ret) {
 		debug("%s: could not find otp device\n", __func__);
diff --git a/board/sifive/hifive_unmatched_fu740/Kconfig b/board/sifive/hifive_unmatched_fu740/Kconfig
new file mode 100644
index 0000000..53c87c6
--- /dev/null
+++ b/board/sifive/hifive_unmatched_fu740/Kconfig
@@ -0,0 +1,50 @@ 
+if TARGET_SIFIVE_UNMATCHED
+
+config SYS_BOARD
+	default "hifive_unmatched_fu740"
+
+config SYS_VENDOR
+	default "sifive"
+
+config SYS_CPU
+	default "fu740"
+
+config SYS_CONFIG_NAME
+	default "sifive-hifive-unmatched-fu740"
+
+config SYS_TEXT_BASE
+	default 0x80200000 if SPL
+	default 0x80000000 if !RISCV_SMODE
+	default 0x80200000 if RISCV_SMODE
+
+config SPL_TEXT_BASE
+	default 0x08000000
+
+config SPL_OPENSBI_LOAD_ADDR
+	default 0x80000000
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+	def_bool y
+	select SIFIVE_FU740
+	select SUPPORT_SPL
+	select RESET_SIFIVE
+	imply CMD_DHCP
+	imply CMD_EXT2
+	imply CMD_EXT4
+	imply CMD_FAT
+	imply CMD_FS_GENERIC
+	imply CMD_GPT
+	imply PARTITION_TYPE_GUID
+	imply CMD_NET
+	imply CMD_PING
+	imply CMD_SF
+	imply DOS_PARTITION
+	imply EFI_PARTITION
+	imply IP_DYN
+	imply ISO_PARTITION
+	imply PHY_LIB
+	imply PHY_MSCC
+	imply SYSRESET
+	imply SYSRESET_GPIO
+
+endif
diff --git a/board/sifive/hifive_unmatched_fu740/MAINTAINERS b/board/sifive/hifive_unmatched_fu740/MAINTAINERS
new file mode 100644
index 0000000..783b20d
--- /dev/null
+++ b/board/sifive/hifive_unmatched_fu740/MAINTAINERS
@@ -0,0 +1,9 @@ 
+SiFive HiFive Unmatched FU740 BOARD
+M:	Paul Walmsley <paul.walmsley@sifive.com>
+M:	Pragnesh Patel <pragnesh.patel@sifive.com>
+M:	Green Wan <green.wan@sifive.com>
+S:	Maintained
+F:	board/sifive/hifive_unmatched_fu740/
+F:	doc/board/sifive/hifive-unmatched-fu740.rst
+F:	include/configs/sifive-hifive-unmatched-fu740.h
+F:	configs/sifive_hifive_unmatched_fu740_defconfig
diff --git a/board/sifive/hifive_unmatched_fu740/Makefile b/board/sifive/hifive_unmatched_fu740/Makefile
new file mode 100644
index 0000000..aeab025
--- /dev/null
+++ b/board/sifive/hifive_unmatched_fu740/Makefile
@@ -0,0 +1,9 @@ 
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright (c) 2020 SiFive, Inc
+
+obj-y   += hifive-unmatched-fu740.o
+
+ifdef CONFIG_SPL_BUILD
+obj-y += spl.o
+endif
diff --git a/board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c b/board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c
new file mode 100644
index 0000000..361bfbf
--- /dev/null
+++ b/board/sifive/hifive_unmatched_fu740/hifive-unmatched-fu740.c
@@ -0,0 +1,24 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020, SiFive Inc
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/arch/cache.h>
+
+int board_init(void)
+{
+	int ret;
+
+	/* enable all cache ways */
+	ret = cache_enable_ways();
+	if (ret) {
+		debug("%s: could not enable cache ways\n", __func__);
+		return ret;
+	}
+	return 0;
+}
diff --git a/board/sifive/hifive_unmatched_fu740/spl.c b/board/sifive/hifive_unmatched_fu740/spl.c
new file mode 100644
index 0000000..d8ee934
--- /dev/null
+++ b/board/sifive/hifive_unmatched_fu740/spl.c
@@ -0,0 +1,85 @@ 
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 SiFive, Inc
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#include <init.h>
+#include <spl.h>
+#include <misc.h>
+#include <log.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/spl.h>
+
+#define GEM_PHY_RESET	SIFIVE_GENERIC_GPIO_NR(0, 12)
+
+#define MODE_SELECT_REG		0x1000
+#define MODE_SELECT_SD		0xb
+#define MODE_SELECT_MASK	GENMASK(3, 0)
+
+int spl_board_init_f(void)
+{
+	int ret;
+
+	ret = spl_soc_init();
+	if (ret) {
+		debug("HiFive Unmatched FU740 SPL init failed: %d\n", ret);
+		return ret;
+	}
+
+	/*
+	 * GEMGXL init VSC8541 PHY reset sequence;
+	 * leave pull-down active for 2ms
+	 */
+	udelay(2000);
+	ret = gpio_request(GEM_PHY_RESET, "gem_phy_reset");
+	if (ret) {
+		debug("gem_phy_reset gpio request failed: %d\n", ret);
+		return ret;
+	}
+
+	/* Set GPIO 12 (PHY NRESET) */
+	ret = gpio_direction_output(GEM_PHY_RESET, 1);
+	if (ret) {
+		debug("gem_phy_reset gpio direction set failed: %d\n", ret);
+		return ret;
+	}
+
+	udelay(1);
+
+	/* Reset PHY again to enter unmanaged mode */
+	gpio_set_value(GEM_PHY_RESET, 0);
+	udelay(1);
+	gpio_set_value(GEM_PHY_RESET, 1);
+	mdelay(15);
+
+	return 0;
+}
+
+u32 spl_boot_device(void)
+{
+	u32 mode_select = readl((void *)MODE_SELECT_REG);
+	u32 boot_device = mode_select & MODE_SELECT_MASK;
+
+	switch (boot_device) {
+	case MODE_SELECT_SD:
+		return BOOT_DEVICE_MMC1;
+	default:
+		debug("Unsupported boot device 0x%x but trying MMC1\n",
+		      boot_device);
+		return BOOT_DEVICE_MMC1;
+	}
+}
+
+#ifdef CONFIG_SPL_LOAD_FIT
+int board_fit_config_name_match(const char *name)
+{
+	/* boot using first FIT config */
+	return 0;
+}
+#endif
diff --git a/configs/sifive_hifive_unmatched_fu740_defconfig b/configs/sifive_hifive_unmatched_fu740_defconfig
new file mode 100644
index 0000000..5ec1ee6
--- /dev/null
+++ b/configs/sifive_hifive_unmatched_fu740_defconfig
@@ -0,0 +1,57 @@ 
+CONFIG_RISCV=y
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x3000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SPL_DM_SPI=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_DEFAULT_DEVICE_TREE="hifive-unmatched-a00"
+CONFIG_TARGET_SIFIVE_UNMATCHED=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_SPL_LOAD_FIT_ADDRESS=0x84000000
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_DM_RESET=y
+CONFIG_SPL_YMODEM_SUPPORT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SPL_CLK=y
+CONFIG_DM_RESET=y
+CONFIG_CMD_PCI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_PCI_PNP=y
+CONFIG_PCIE_SIFIVE_FU740=y
+CONFIG_NVME=y
+CONFIG_DM_ETH=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
+CONFIG_USB=y
+CONFIG_CMD_USB=y
+CONFIG_DM_USB=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PCI=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_GENERIC=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_GENERIC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_NVME=y
+CONFIG_SYS_USB_EVENT_POLL=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_EEPROM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_I2C=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_OCORES=y
+CONFIG_CLK_SIFIVE_PRCI=y
+ONFIG_DM_PWM=y
+CONFIG_PWM_SIFIVE=y
+CONFIG_CMD_PWM=y
diff --git a/doc/board/sifive/fu540.rst b/doc/board/sifive/fu540.rst
index 4e4c852..1ce9ab1 100644
--- a/doc/board/sifive/fu540.rst
+++ b/doc/board/sifive/fu540.rst
@@ -12,7 +12,6 @@  of running Linux.
 
 Mainline support
 ----------------
-
 The support for following drivers are already enabled:
 
 1. SiFive UART Driver.
@@ -25,7 +24,7 @@  Booting from MMC using FSBL
 ---------------------------
 
 Building
-~~~~~~~~
+--------
 
 1. Add the RISC-V toolchain to your PATH.
 2. Setup ARCH & cross compilation environment variable:
@@ -38,7 +37,7 @@  Building
 4. make
 
 Flashing
-~~~~~~~~
+--------
 
 The current U-Boot port is supported in S-mode only and loaded from DRAM.
 
@@ -64,12 +63,11 @@  copied to the first partition of the sdcard.
     sudo dd if=<prior_stage_firmware_binary> of=/dev/disk2s1 bs=1024
 
 Booting
-~~~~~~~
-
+-------
 Once you plugin the sdcard and power up, you should see the U-Boot prompt.
 
 Sample boot log from HiFive Unleashed board
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------------------
 
 .. code-block:: none
 
@@ -419,7 +417,7 @@  Booting from MMC using U-Boot SPL
 ---------------------------------
 
 Building
-~~~~~~~~
+--------
 
 Before building U-Boot SPL, OpenSBI must be built first. OpenSBI can be
 cloned and built for FU540 as below:
@@ -443,7 +441,7 @@  This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
 
 
 Flashing
-~~~~~~~~
+--------
 
 ZSBL loads the U-Boot SPL (u-boot-spl.bin) from a partition with GUID type
 5B193300-FC78-40CD-8002-E86C45580B47
@@ -473,12 +471,11 @@  Program the SD card
 	sudo dd if=u-boot.itb of=/dev/sda seek=2082
 
 Booting
-~~~~~~~
-
+-------
 Once you plugin the sdcard and power up, you should see the U-Boot prompt.
 
 Sample boot log from HiFive Unleashed board
-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+-------------------------------------------
 
 .. code-block:: none
 
diff --git a/doc/board/sifive/hifive_unmatched_fu740.rst b/doc/board/sifive/hifive_unmatched_fu740.rst
new file mode 100644
index 0000000..6670df5
--- /dev/null
+++ b/doc/board/sifive/hifive_unmatched_fu740.rst
@@ -0,0 +1,532 @@ 
+.. SPDX-License-Identifier: GPL-2.0+
+
+HiFive Unmatched
+================
+
+FU740-C000 RISC-V SoC
+---------------------
+The FU740-C000 is a 4+1 64-bit RISC-V core SoC from SiFive.
+
+The HiFive Unmatched development platform is based on FU740-C000 and capable
+of running Linux.
+
+Mainline support
+----------------
+The support for following drivers are already enabled:
+
+1. SiFive UART Driver.
+2. SiFive PRCI Driver for clock.
+3. Cadence MACB ethernet driver for networking support.
+4. SiFive SPI Driver.
+5. MMC SPI Driver for MMC/SD support.
+
+Booting from MMC using u-boot-spl
+---------------------------
+
+Building
+--------
+
+1. Add the RISC-V toolchain to your PATH.
+2. Setup ARCH & cross compilation environment variable:
+
+.. code-block:: none
+
+   export CROSS_COMPILE=<riscv64 toolchain prefix>
+
+3. make sifive_hifive_unmatched_fu740_defconfig
+4. make
+
+Flashing
+--------
+
+The current U-Boot port is supported in S-mode only and loaded from DRAM.
+
+A prior stage M-mode firmware/bootloader (e.g OpenSBI) is required to
+boot the u-boot.bin in S-mode and provide M-mode runtime services.
+
+Currently, the u-boot.bin is used as a payload of the OpenSBI FW_PAYLOAD
+firmware. We need to compile OpenSBI with below command:
+
+.. code-block:: none
+
+	make PLATFORM=generic FW_PAYLOAD_PATH=<path to u-boot-dtb.bin>
+
+More detailed description of steps required to build FW_PAYLOAD firmware
+is beyond the scope of this document. Please refer OpenSBI documenation.
+(Note: OpenSBI git repo is at https://github.com/riscv/opensbi.git)
+
+Once the prior stage firmware/bootloader binary is generated, it should be
+copied to the first partition of the sdcard.
+
+.. code-block:: none
+
+    sudo dd if=<prior_stage_firmware_binary> of=/dev/disk2s1 bs=1024
+
+Booting
+-------
+Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+
+Sample boot log from HiFive Unmatched board
+-------------------------------------------
+
+.. code-block:: none
+
+   U-Boot 2019.07-00024-g350ff02f5b (Jul 22 2019 - 11:45:02 +0530)
+
+   CPU:   rv64imafdc
+   Model: SiFive HiFive Unmatched A00
+   DRAM:  8 GiB
+   MMC:   spi@10050000:mmc@0: 0
+   In:    serial@10010000
+   Out:   serial@10010000
+   Err:   serial@10010000
+   Net:   eth0: ethernet@10090000
+   Hit any key to stop autoboot:  0
+   => version
+   U-Boot 2019.07-00024-g350ff02f5b (Jul 22 2019 - 11:45:02 +0530)
+
+   riscv64-linux-gcc.br_real (Buildroot 2018.11-rc2-00003-ga0787e9) 8.2.0
+   GNU ld (GNU Binutils) 2.31.1
+   => mmc info
+   Device: spi@10050000:mmc@0
+   Manufacturer ID: 3
+   OEM: 5344
+   Name: SU08G
+   Bus Speed: 20000000
+   Mode: SD Legacy
+   Rd Block Len: 512
+   SD version 2.0
+   High Capacity: Yes
+   Capacity: 7.4 GiB
+   Bus Width: 1-bit
+   Erase Group Size: 512 Bytes
+   => mmc part
+
+   Partition Map for MMC device 0  --   Partition Type: EFI
+
+   Part    Start LBA       End LBA         Name
+           Attributes
+           Type GUID
+           Partition GUID
+     1     0x00000800      0x000107ff      "bootloader"
+           attrs:  0x0000000000000000
+           type:   2e54b353-1271-4842-806f-e436d6af6985
+           guid:   393bbd36-7111-491c-9869-ce24008f6403
+     2     0x00040800      0x00ecdfde      ""
+           attrs:  0x0000000000000000
+           type:   0fc63daf-8483-4772-8e79-3d69d8477de4
+           guid:   7fc9a949-5480-48c7-b623-04923080757f
+
+Now you can configure your networking, tftp server and use tftp boot method to
+load uImage.
+
+.. code-block:: none
+
+   => setenv ipaddr 10.206.7.133
+   => setenv netmask 255.255.252.0
+   => setenv serverip 10.206.4.143
+   => setenv gateway 10.206.4.1
+
+If you want to use a flat kernel image such as Image file
+
+.. code-block:: none
+
+   => tftpboot ${kernel_addr_r} /sifive/fu740/Image
+   ethernet@10090000: PHY present at 0
+   ethernet@10090000: Starting autonegotiation...
+   ethernet@10090000: Autonegotiation complete
+   ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3c00)
+   Using ethernet@10090000 device
+   TFTP from server 10.206.4.143; our IP address is 10.206.7.133
+   Filename '/sifive/fu740/Image'.
+   Load address: 0x84000000
+   Loading: #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            ##########################################
+            1.2 MiB/s
+   done
+   Bytes transferred = 8867100 (874d1c hex)
+
+Or if you want to use a compressed kernel image file such as Image.gz
+
+.. code-block:: none
+
+   => tftpboot ${kernel_addr_r} /sifive/fu740/Image.gz
+   ethernet@10090000: PHY present at 0
+   ethernet@10090000: Starting autonegotiation...
+   ethernet@10090000: Autonegotiation complete
+   ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3c00)
+   Using ethernet@10090000 device
+   TFTP from server 10.206.4.143; our IP address is 10.206.7.133
+   Filename '/sifive/fu740/Image.gz'.
+   Load address: 0x84000000
+   Loading: #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            ##########################################
+            1.2 MiB/s
+   done
+   Bytes transferred = 4809458 (4962f2 hex)
+   =>setenv kernel_comp_addr_r 0x90000000
+   =>setenv kernel_comp_size 0x500000
+
+By this time, correct kernel image is loaded and required environment variables
+are set. You can proceed to load the ramdisk and device tree from the tftp server
+as well.
+
+.. code-block:: none
+
+   => tftpboot ${ramdisk_addr_r} /sifive/fu740/uRamdisk
+   ethernet@10090000: PHY present at 0
+   ethernet@10090000: Starting autonegotiation...
+   ethernet@10090000: Autonegotiation complete
+   ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x3c00)
+   Using ethernet@10090000 device
+   TFTP from server 10.206.4.143; our IP address is 10.206.7.133
+   Filename '/sifive/fu740/uRamdisk'.
+   Load address: 0x88300000
+   Loading: #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            #################################################################
+            ##############
+            418.9 KiB/s
+   done
+   Bytes transferred = 2398272 (249840 hex)
+   => tftpboot ${fdt_addr_r} /sifive/fu740/hifive-unmatched-a00.dtb
+   ethernet@10090000: PHY present at 0
+   ethernet@10090000: Starting autonegotiation...
+   ethernet@10090000: Autonegotiation complete
+   ethernet@10090000: link up, 1000Mbps full-duplex (lpa: 0x7c00)
+   Using ethernet@10090000 device
+   TFTP from server 10.206.4.143; our IP address is 10.206.7.133
+   Filename '/sifive/fu740/hifive-unmatched-a00.dtb'.
+   Load address: 0x88000000
+   Loading: ##
+            1000 Bytes/s
+   done
+   Bytes transferred = 5614 (15ee hex)
+   => setenv bootargs "root=/dev/ram rw console=ttySIF0 ip=dhcp earlycon=sbi"
+   => booti ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}
+   ## Loading init Ramdisk from Legacy Image at 88300000 ...
+      Image Name:   Linux RootFS
+      Image Type:   RISC-V Linux RAMDisk Image (uncompressed)
+      Data Size:    2398208 Bytes = 2.3 MiB
+      Load Address: 00000000
+      Entry Point:  00000000
+      Verifying Checksum ... OK
+   ## Flattened Device Tree blob at 88000000
+      Booting using the fdt blob at 0x88000000
+      Using Device Tree in place at 0000000088000000, end 00000000880045ed
+
+   Starting kernel ...
+
+   [    0.000000] OF: fdt: Ignoring memory range 0x80000000 - 0x80200000
+   [    0.000000] Linux version 5.3.0-rc1-00003-g460ac558152f (anup@anup-lab-machine) (gcc version 8.2.0 (Buildroot 2018.11-rc2-00003-ga0787e9)) #6 SMP Mon Jul 22 10:01:01 IST 2019
+   [    0.000000] earlycon: sbi0 at I/O port 0x0 (options '')
+   [    0.000000] printk: bootconsole [sbi0] enabled
+   [    0.000000] Initial ramdisk at: 0x(____ptrval____) (2398208 bytes)
+   [    0.000000] Zone ranges:
+   [    0.000000]   DMA32    [mem 0x0000000080200000-0x00000000ffffffff]
+   [    0.000000]   Normal   [mem 0x0000000100000000-0x000000027fffffff]
+   [    0.000000] Movable zone start for each node
+   [    0.000000] Early memory node ranges
+   [    0.000000]   node   0: [mem 0x0000000080200000-0x000000027fffffff]
+   [    0.000000] Initmem setup node 0 [mem 0x0000000080200000-0x000000027fffffff]
+   [    0.000000] software IO TLB: mapped [mem 0xfbfff000-0xfffff000] (64MB)
+   [    0.000000] CPU with hartid=0 is not available
+   [    0.000000] CPU with hartid=0 is not available
+   [    0.000000] elf_hwcap is 0x112d
+   [    0.000000] percpu: Embedded 18 pages/cpu s34584 r8192 d30952 u73728
+   [    0.000000] Built 1 zonelists, mobility grouping on.  Total pages: 2067975
+   [    0.000000] Kernel command line: root=/dev/ram rw console=ttySIF0 ip=dhcp earlycon=sbi
+   [    0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
+   [    0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
+   [    0.000000] Sorting __ex_table...
+   [    0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
+   [    0.000000] Memory: 8182308K/8386560K available (5916K kernel code, 368K rwdata, 1840K rodata, 213K init, 304K bss, 204252K reserved, 0K cma-reserved)
+   [    0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
+   [    0.000000] rcu: Hierarchical RCU implementation.
+   [    0.000000] rcu:     RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
+   [    0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
+   [    0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
+   [    0.000000] NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
+   [    0.000000] plic: mapped 53 interrupts with 4 handlers for 9 contexts.
+   [    0.000000] riscv_timer_init_dt: Registering clocksource cpuid [0] hartid [1]
+   [    0.000000] clocksource: riscv_clocksource: mask: 0xffffffffffffffff max_cycles: 0x1d854df40, max_idle_ns: 3526361616960 ns
+   [    0.000006] sched_clock: 64 bits at 1000kHz, resolution 1000ns, wraps every 2199023255500ns
+   [    0.008559] Console: colour dummy device 80x25
+   [    0.012989] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.00 BogoMIPS (lpj=4000)
+   [    0.023104] pid_max: default: 32768 minimum: 301
+   [    0.028273] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
+   [    0.035765] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
+   [    0.045307] rcu: Hierarchical SRCU implementation.
+   [    0.049875] smp: Bringing up secondary CPUs ...
+   [    0.055729] smp: Brought up 1 node, 4 CPUs
+   [    0.060599] devtmpfs: initialized
+   [    0.064819] random: get_random_u32 called from bucket_table_alloc.isra.10+0x4e/0x160 with crng_init=0
+   [    0.073720] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
+   [    0.083176] futex hash table entries: 1024 (order: 4, 65536 bytes, linear)
+   [    0.090721] NET: Registered protocol family 16
+   [    0.106319] vgaarb: loaded
+   [    0.108670] SCSI subsystem initialized
+   [    0.112515] usbcore: registered new interface driver usbfs
+   [    0.117758] usbcore: registered new interface driver hub
+   [    0.123167] usbcore: registered new device driver usb
+   [    0.128905] clocksource: Switched to clocksource riscv_clocksource
+   [    0.141239] NET: Registered protocol family 2
+   [    0.145506] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
+   [    0.153754] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
+   [    0.163466] TCP bind hash table entries: 65536 (order: 8, 1048576 bytes, linear)
+   [    0.173468] TCP: Hash tables configured (established 65536 bind 65536)
+   [    0.179739] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
+   [    0.186627] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
+   [    0.194117] NET: Registered protocol family 1
+   [    0.198417] RPC: Registered named UNIX socket transport module.
+   [    0.203887] RPC: Registered udp transport module.
+   [    0.208664] RPC: Registered tcp transport module.
+   [    0.213429] RPC: Registered tcp NFSv4.1 backchannel transport module.
+   [    0.219944] PCI: CLS 0 bytes, default 64
+   [    0.224170] Unpacking initramfs...
+   [    0.262347] Freeing initrd memory: 2336K
+   [    0.266531] workingset: timestamp_bits=62 max_order=21 bucket_order=0
+   [    0.280406] NFS: Registering the id_resolver key type
+   [    0.284798] Key type id_resolver registered
+   [    0.289048] Key type id_legacy registered
+   [    0.293114] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
+   [    0.300262] NET: Registered protocol family 38
+   [    0.304432] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
+   [    0.311862] io scheduler mq-deadline registered
+   [    0.316461] io scheduler kyber registered
+   [    0.356421] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
+   [    0.363004] 10010000.serial: ttySIF0 at MMIO 0x10010000 (irq = 4, base_baud = 0) is a SiFive UART v0
+   [    0.371468] printk: console [ttySIF0] enabled
+   [    0.371468] printk: console [ttySIF0] enabled
+   [    0.380223] printk: bootconsole [sbi0] disabled
+   [    0.380223] printk: bootconsole [sbi0] disabled
+   [    0.389589] 10011000.serial: ttySIF1 at MMIO 0x10011000 (irq = 1, base_baud = 0) is a SiFive UART v0
+   [    0.398680] [drm] radeon kernel modesetting enabled.
+   [    0.412395] loop: module loaded
+   [    0.415214] sifive_spi 10040000.spi: mapped; irq=3, cs=1
+   [    0.420628] sifive_spi 10050000.spi: mapped; irq=5, cs=1
+   [    0.425897] libphy: Fixed MDIO Bus: probed
+   [    0.429964] macb 10090000.ethernet: Registered clk switch 'sifive-gemgxl-mgmt'
+   [    0.436743] macb: GEM doesn't support hardware ptp.
+   [    0.441621] libphy: MACB_mii_bus: probed
+   [    0.601316] Microsemi VSC8541 SyncE 10090000.ethernet-ffffffff:00: attached PHY driver [Microsemi VSC8541 SyncE] (mii_bus:phy_addr=10090000.ethernet-ffffffff:00, irq=POLL)
+   [    0.615857] macb 10090000.ethernet eth0: Cadence GEM rev 0x10070109 at 0x10090000 irq 6 (70:b3:d5:92:f2:f3)
+   [    0.625634] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
+   [    0.631381] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
+   [    0.637382] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
+   [    0.643799] ehci-pci: EHCI PCI platform driver
+   [    0.648261] ehci-platform: EHCI generic platform driver
+   [    0.653497] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
+   [    0.659599] ohci-pci: OHCI PCI platform driver
+   [    0.664055] ohci-platform: OHCI generic platform driver
+   [    0.669448] usbcore: registered new interface driver uas
+   [    0.674575] usbcore: registered new interface driver usb-storage
+   [    0.680642] mousedev: PS/2 mouse device common for all mice
+   [    0.709493] mmc_spi spi1.0: SD/MMC host mmc0, no DMA, no WP, no poweroff, cd polling
+   [    0.716615] usbcore: registered new interface driver usbhid
+   [    0.722023] usbhid: USB HID core driver
+   [    0.726738] NET: Registered protocol family 10
+   [    0.731359] Segment Routing with IPv6
+   [    0.734332] sit: IPv6, IPv4 and MPLS over IPv4 tunneling driver
+   [    0.740687] NET: Registered protocol family 17
+   [    0.744660] Key type dns_resolver registered
+   [    0.806775] mmc0: host does not support reading read-only switch, assuming write-enable
+   [    0.814020] mmc0: new SDHC card on SPI
+   [    0.820137] mmcblk0: mmc0:0000 SU08G 7.40 GiB
+   [    0.850220]  mmcblk0: p1 p2
+   [    3.821524] macb 10090000.ethernet eth0: link up (1000/Full)
+   [    3.828938] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready
+   [    3.848919] Sending DHCP requests .., OK
+   [    6.252076] IP-Config: Got DHCP answer from 10.206.4.1, my address is 10.206.7.133
+   [    6.259624] IP-Config: Complete:
+   [    6.262831]      device=eth0, hwaddr=70:b3:d5:92:f2:f3, ipaddr=10.206.7.133, mask=255.255.252.0, gw=10.206.4.1
+   [    6.272809]      host=dhcp-10-206-7-133, domain=sdcorp.global.sandisk.com, nis-domain=(none)
+   [    6.281228]      bootserver=10.206.126.11, rootserver=10.206.126.11, rootpath=
+   [    6.281232]      nameserver0=10.86.1.1, nameserver1=10.86.2.1
+   [    6.294179]      ntpserver0=10.86.1.1, ntpserver1=10.86.2.1
+   [    6.301026] Freeing unused kernel memory: 212K
+   [    6.304683] This architecture does not have kernel memory protection.
+   [    6.311121] Run /init as init process
+              _  _
+             | ||_|
+             | | _ ____  _   _  _  _
+             | || |  _ \| | | |\ \/ /
+             | || | | | | |_| |/    \
+             |_||_|_| |_|\____|\_/\_/
+
+                  Busybox Rootfs
+
+   Please press Enter to activate this console.
+   / #
+
+Booting from MMC using U-Boot SPL
+---------------------------------
+
+Building
+--------
+
+Before building U-Boot SPL, OpenSBI must be built first. OpenSBI can be
+cloned and built for FU740 as below:
+
+.. code-block:: console
+
+	git clone https://github.com/riscv/opensbi.git
+	cd opensbi
+	make PLATFORM=generic
+	export OPENSBI=<path to opensbi/build/platform/generic/firmware/fw_dynamic.bin>
+
+Now build the U-Boot SPL and U-Boot proper
+
+.. code-block:: console
+
+	cd <U-Boot-dir>
+	make sifive_hifive_unmatched_fu740_defconfig
+	make
+
+This will generate spl/u-boot-spl.bin and FIT image (u-boot.itb)
+
+
+Flashing
+--------
+
+ZSBL loads the U-Boot SPL (u-boot-spl.bin) from a partition with GUID type
+5B193300-FC78-40CD-8002-E86C45580B47
+
+U-Boot SPL expects a U-Boot FIT image (u-boot.itb) from a partition with GUID
+type 2E54B353-1271-4842-806F-E436D6AF6985
+
+FIT image (u-boot.itb) is a combination of fw_dynamic.bin, u-boot-nodtb.bin and
+device tree blob (hifive-unmatched-a00.dtb)
+
+Format the SD card (make sure the disk has GPT, otherwise use gdisk to switch)
+
+.. code-block:: none
+
+	# sudo sgdisk --clear \
+	> --set-alignment=2 \
+	> --new=1:34:2081 --change-name=1:loader1 --typecode=1:5B193300-FC78-40CD-8002-E86C45580B47 \
+	> --new=2:2082:10273 --change-name=2:loader2 --typecode=2:2E54B353-1271-4842-806F-E436D6AF6985 \
+	> --new=3:10274: --change-name=3:rootfs --typecode=3:0FC63DAF-8483-4772-8E79-3D69D8477DE4 \
+	> /dev/sda
+
+Program the SD card
+
+.. code-block:: none
+
+	sudo dd if=spl/u-boot-spl.bin of=/dev/sda seek=34
+	sudo dd if=u-boot.itb of=/dev/sda seek=2082
+
+Booting
+-------
+Once you plugin the sdcard and power up, you should see the U-Boot prompt.
+
+Sample boot log from HiFive Unmatched board
+-------------------------------------------
+
+.. code-block:: none
+
+        U-Boot SPL 2021.04-rc3 (Mar 11 2021 - 08:07:46 +0000)
+        Trying to boot from MMC1
+
+
+        U-Boot 2021.04-rc3 (Mar 11 2021 - 08:07:46 +0000)
+
+        CPU:   rv64imafdc
+        Model: SiFive HiFive Unmatched A00
+        DRAM:  16 GiB
+        MMC:   spi@10050000:mmc@0: 0
+        In:    serial@10010000
+        Out:   serial@10010000
+        Err:   serial@10010000
+        Model: SiFive HiFive Unmatched A00
+        Net:
+        Error: ethernet@10090000 address not set.
+        No ethernet found.
+
+        Hit any key to stop autoboot:  0
+        => version
+        U-Boot 2021.04-rc3 (Mar 11 2021 - 08:07:46 +0000)
+
+        riscv64-oe-linux-gcc (GCC) 10.2.0
+        GNU ld (GNU Binutils) 2.35.0.20200730
+        => mmc part
+
+        Partition Map for MMC device 0  --   Partition Type: EFI
+
+        Part    Start LBA       End LBA         Name
+        Attributes
+        Type GUID
+        Partition GUID
+        1     0x00000022      0x00000821      "primary"
+              attrs:  0x0000000000000000
+              type:   5b193300-fc78-40cd-8002-e86c45580b47
+              guid:   f4b7c671-63ec-4f3b-8f26-3f10407df3c7
+        2     0x00000822      0x00002821      "primary"
+              attrs:  0x0000000000000000
+              type:   2e54b353-1271-4842-806f-e436d6af6985
+              guid:   e48d9a09-ff68-4219-abb4-62917290de3c
+        3     0x00004000      0x00044fff      "boot"
+              attrs:  0x0000000000000004
+              type:   ebd0a0a2-b9e5-4433-87c0-68b6b72699c7
+              type:   data
+              guid:   6af708a6-0e40-4476-a900-cd59954034f1
+        4     0x00046000      0x03b723de      "root"
+              attrs:  0x0000000000000000
+              type:   0fc63daf-8483-4772-8e79-3d69d8477de4
+              type:   linux
+              guid:   038165a5-b704-4d96-9bc4-2533803c6620
+
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index f5b3f88..33bbbd5 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -166,7 +166,7 @@  config RESET_IPQ419
 
 config RESET_SIFIVE
 	bool "Reset Driver for SiFive SoC's"
-	depends on DM_RESET && CLK_SIFIVE_FU540_PRCI && TARGET_SIFIVE_FU540
+	depends on DM_RESET && CLK_SIFIVE_PRCI && (TARGET_SIFIVE_FU540 || TARGET_SIFIVE_HIFIVE_UNMATCHED_FU740)
 	default y
 	help
 	  PRCI module within SiFive SoC's provides mechanism to reset
diff --git a/include/configs/sifive-fu540.h b/include/configs/sifive-fu540.h
index 0d69d1c..c1c79db 100644
--- a/include/configs/sifive-fu540.h
+++ b/include/configs/sifive-fu540.h
@@ -36,11 +36,6 @@ 
 
 #define CONFIG_STANDALONE_LOAD_ADDR	0x80200000
 
-#define RISCV_MMODE_TIMERBASE		0x2000000
-#define RISCV_MMODE_TIMER_FREQ		1000000
-
-#define RISCV_SMODE_TIMER_FREQ		1000000
-
 /* Environment options */
 
 #ifndef CONFIG_SPL_BUILD
diff --git a/include/configs/sifive-hifive-unmatched-fu740.h b/include/configs/sifive-hifive-unmatched-fu740.h
new file mode 100644
index 0000000..b59df9c
--- /dev/null
+++ b/include/configs/sifive-hifive-unmatched-fu740.h
@@ -0,0 +1,88 @@ 
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (c) 2020 SiFive, Inc
+ *
+ * Authors:
+ *   Pragnesh Patel <pragnesh.patel@sifive.com>
+ */
+
+#ifndef __SIFIVE_UNMATCHED_H
+#define __SIFIVE_UNMATCHED_H
+
+#include <linux/sizes.h>
+
+#ifdef CONFIG_SPL
+
+#define CONFIG_SPL_MAX_SIZE		0x00100000
+#define CONFIG_SPL_BSS_START_ADDR	0x85000000
+#define CONFIG_SPL_BSS_MAX_SIZE		0x00100000
+#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SPL_BSS_START_ADDR + \
+					 CONFIG_SPL_BSS_MAX_SIZE)
+#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00100000
+
+#define CONFIG_SPL_STACK	(0x08000000 + 0x001D0000 - \
+				 GENERATED_GBL_DATA_SIZE)
+
+#endif
+
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_2M)
+
+#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + SZ_2M)
+
+#define CONFIG_SYS_MALLOC_LEN		SZ_8M
+
+#define CONFIG_SYS_BOOTM_LEN		SZ_64M
+
+#define CONFIG_STANDALONE_LOAD_ADDR	0x80200000
+
+#define CONFIG_SYS_PCI_64BIT		1	/* enable 64-bit resources */
+
+#define CONFIG_SYS_CACHELINE_SIZE	64
+
+#define CONFIG_USB_OHCI_NEW
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS     4
+
+/* Environment options */
+
+#ifndef CONFIG_SPL_BUILD
+#define BOOT_TARGET_DEVICES(func) \
+	func(NVME, nvme, 0) \
+	func(USB, usb, 0) \
+	func(MMC, mmc, 0) \
+	func(PXE, pxe, na) \
+	func(DHCP, dhcp, na)
+
+#include <config_distro_bootcmd.h>
+
+#define TYPE_GUID_LOADER1	"5B193300-FC78-40CD-8002-E86C45580B47"
+#define TYPE_GUID_LOADER2	"2E54B353-1271-4842-806F-E436D6AF6985"
+#define TYPE_GUID_SYSTEM	"0FC63DAF-8483-4772-8E79-3D69D8477DE4"
+
+#define PARTS_DEFAULT \
+	"name=loader1,start=17K,size=1M,type=${type_guid_gpt_loader1};" \
+	"name=loader2,size=4MB,type=${type_guid_gpt_loader2};" \
+	"name=system,size=-,bootable,type=${type_guid_gpt_system};"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"fdt_high=0xffffffffffffffff\0" \
+	"initrd_high=0xffffffffffffffff\0" \
+	"kernel_addr_r=0x84000000\0" \
+	"fdt_addr_r=0x88000000\0" \
+	"scriptaddr=0x88100000\0" \
+	"pxefile_addr_r=0x88200000\0" \
+	"ramdisk_addr_r=0x88300000\0" \
+	"kernel_comp_addr_r=0x90000000\0" \
+	"kernel_comp_size=0x4000000\0" \
+	"type_guid_gpt_loader1=" TYPE_GUID_LOADER1 "\0" \
+	"type_guid_gpt_loader2=" TYPE_GUID_LOADER2 "\0" \
+	"type_guid_gpt_system=" TYPE_GUID_SYSTEM "\0" \
+	"partitions=" PARTS_DEFAULT "\0" \
+	BOOTENV
+
+#define CONFIG_PREBOOT \
+	"setenv fdt_addr ${fdtcontroladdr};" \
+	"fdt addr ${fdtcontroladdr};"
+#endif /* CONFIG_SPL_BUILD */
+
+#endif /* __SIFIVE_UNMATCHED_H */