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[44.242.66.180]) by smtp.gmail.com with ESMTPSA id w26sm2010399edq.46.2021.02.07.07.11.55 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 07 Feb 2021 07:11:58 -0800 (PST) From: Bin Meng To: Simon Glass , Alexander Graf , Priyanka Jain Cc: Tom Rini , U-Boot Mailing List Subject: [PATCH 04/26] ppc: qemu: Support non-identity PCI bus address Date: Sun, 7 Feb 2021 23:11:04 +0800 Message-Id: <1612710687-56493-5-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1612710687-56493-1-git-send-email-bmeng.cn@gmail.com> References: <1612710687-56493-1-git-send-email-bmeng.cn@gmail.com> X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.102.3 at phobos.denx.de X-Virus-Status: Clean When QEMU originally supported the ppce500 machine back in Jan 2014, it was created with a 1:1 mapping of PCI bus address. Things seemed to change rapidly that in Nov 2014 with the following QEMU commits: commit e6b4e5f4795b ("PPC: e500: Move CCSR and MMIO space to upper end of address space") and commit cb3778a0455a ("PPC: e500 pci host: Add support for ATMUs") the PCI memory and IO physical address were moved to beyond 4 GiB, but PCI bus address remained below 4 GiB, hence a non-identity mapping was created. Unfortunately corresponding U-Boot updates were missed along with the QEMU changes and the U-Boot QEMU ppce500 PCI support has been broken since then. This commit makes the PCI (non-DM version) work again. Signed-off-by: Bin Meng --- board/freescale/qemu-ppce500/qemu-ppce500.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c b/board/freescale/qemu-ppce500/qemu-ppce500.c index 3395377..f82501c 100644 --- a/board/freescale/qemu-ppce500/qemu-ppce500.c +++ b/board/freescale/qemu-ppce500/qemu-ppce500.c @@ -84,20 +84,24 @@ int checkboard(void) } static int pci_map_region(void *fdt, int pci_node, int range_id, - phys_size_t *ppaddr, pci_addr_t *pvaddr, - pci_size_t *psize, ulong *pmap_addr) + phys_addr_t *pbaddr, phys_size_t *ppaddr, + pci_addr_t *pvaddr, pci_size_t *psize, + ulong *pmap_addr) { - uint64_t addr; + uint64_t baddr; + uint64_t paddr; uint64_t size; ulong map_addr; int r; - r = fdt_read_range(fdt, pci_node, range_id, NULL, &addr, &size); + r = fdt_read_range(fdt, pci_node, range_id, &baddr, &paddr, &size); if (r) return r; + if (pbaddr) + *pbaddr = baddr; if (ppaddr) - *ppaddr = addr; + *ppaddr = paddr; if (psize) *psize = size; @@ -114,7 +118,7 @@ static int pci_map_region(void *fdt, int pci_node, int range_id, return -1; /* Map virtual memory for range */ - assert(!tlb_map_range(map_addr, addr, size, TLB_MAP_IO)); + assert(!tlb_map_range(map_addr, paddr, size, TLB_MAP_IO)); *pmap_addr = map_addr + size; if (pvaddr) @@ -165,24 +169,19 @@ void pci_init_board(void) pci_info.regs = fdt_translate_address(fdt, pci_node, reg); /* Map MMIO range */ - r = pci_map_region(fdt, pci_node, 0, &pci_info.mem_phys, NULL, + r = pci_map_region(fdt, pci_node, 0, &pci_info.mem_bus, + &pci_info.mem_phys, NULL, &pci_info.mem_size, &map_addr); if (r) break; /* Map PIO range */ - r = pci_map_region(fdt, pci_node, 1, &pci_info.io_phys, NULL, + r = pci_map_region(fdt, pci_node, 1, &pci_info.io_bus, + &pci_info.io_phys, NULL, &pci_info.io_size, &map_addr); if (r) break; - /* - * The PCI framework finds virtual addresses for the buses - * through our address map, so tell it the physical addresses. - */ - pci_info.mem_bus = pci_info.mem_phys; - pci_info.io_bus = pci_info.io_phys; - /* Instantiate */ pci_info.pci_num = pci_num + 1;