@@ -84,20 +84,24 @@ int checkboard(void)
}
static int pci_map_region(void *fdt, int pci_node, int range_id,
- phys_size_t *ppaddr, pci_addr_t *pvaddr,
- pci_size_t *psize, ulong *pmap_addr)
+ phys_addr_t *pbaddr, phys_size_t *ppaddr,
+ pci_addr_t *pvaddr, pci_size_t *psize,
+ ulong *pmap_addr)
{
- uint64_t addr;
+ uint64_t baddr;
+ uint64_t paddr;
uint64_t size;
ulong map_addr;
int r;
- r = fdt_read_range(fdt, pci_node, range_id, NULL, &addr, &size);
+ r = fdt_read_range(fdt, pci_node, range_id, &baddr, &paddr, &size);
if (r)
return r;
+ if (pbaddr)
+ *pbaddr = baddr;
if (ppaddr)
- *ppaddr = addr;
+ *ppaddr = paddr;
if (psize)
*psize = size;
@@ -114,7 +118,7 @@ static int pci_map_region(void *fdt, int pci_node, int range_id,
return -1;
/* Map virtual memory for range */
- assert(!tlb_map_range(map_addr, addr, size, TLB_MAP_IO));
+ assert(!tlb_map_range(map_addr, paddr, size, TLB_MAP_IO));
*pmap_addr = map_addr + size;
if (pvaddr)
@@ -165,24 +169,19 @@ void pci_init_board(void)
pci_info.regs = fdt_translate_address(fdt, pci_node, reg);
/* Map MMIO range */
- r = pci_map_region(fdt, pci_node, 0, &pci_info.mem_phys, NULL,
+ r = pci_map_region(fdt, pci_node, 0, &pci_info.mem_bus,
+ &pci_info.mem_phys, NULL,
&pci_info.mem_size, &map_addr);
if (r)
break;
/* Map PIO range */
- r = pci_map_region(fdt, pci_node, 1, &pci_info.io_phys, NULL,
+ r = pci_map_region(fdt, pci_node, 1, &pci_info.io_bus,
+ &pci_info.io_phys, NULL,
&pci_info.io_size, &map_addr);
if (r)
break;
- /*
- * The PCI framework finds virtual addresses for the buses
- * through our address map, so tell it the physical addresses.
- */
- pci_info.mem_bus = pci_info.mem_phys;
- pci_info.io_bus = pci_info.io_phys;
-
/* Instantiate */
pci_info.pci_num = pci_num + 1;
When QEMU originally supported the ppce500 machine back in Jan 2014, it was created with a 1:1 mapping of PCI bus address. Things seemed to change rapidly that in Nov 2014 with the following QEMU commits: commit e6b4e5f4795b ("PPC: e500: Move CCSR and MMIO space to upper end of address space") and commit cb3778a0455a ("PPC: e500 pci host: Add support for ATMUs") the PCI memory and IO physical address were moved to beyond 4 GiB, but PCI bus address remained below 4 GiB, hence a non-identity mapping was created. Unfortunately corresponding U-Boot updates were missed along with the QEMU changes and the U-Boot QEMU ppce500 PCI support has been broken since then. This commit makes the PCI (non-DM version) work again. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- board/freescale/qemu-ppce500/qemu-ppce500.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-)