[20/26] pci: mpc85xx: Support 64-bit bus and cpu address

Message ID	1612710687-56493-21-git-send-email-bmeng.cn@gmail.com
State	Superseded
Delegated to:	Priyanka Jain
Headers	show Return-Path: <u-boot-bounces@lists.denx.de> From: Bin Meng <bmeng.cn@gmail.com> To: Simon Glass <sjg@chromium.org>, Alexander Graf <agraf@csgraf.de>, Priyanka Jain <priyanka.jain@nxp.com> Cc: Tom Rini <trini@konsulko.com>, U-Boot Mailing List <u-boot@lists.denx.de>, Heiko Schocher <hs@denx.de> Subject: [PATCH 20/26] pci: mpc85xx: Support 64-bit bus and cpu address Date: Sun, 7 Feb 2021 23:11:20 +0800 Message-Id: <1612710687-56493-21-git-send-email-bmeng.cn@gmail.com> In-Reply-To: <1612710687-56493-1-git-send-email-bmeng.cn@gmail.com> References: <1612710687-56493-1-git-send-email-bmeng.cn@gmail.com> Precedence: list Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de>
Series	ppc: qemu: Convert qemu-ppce500 to driver model \| expand [00/26] ppc: qemu: Convert qemu-ppce500 to driver model [01/26] Revert "pci: pci-uclass: Dynamically allocate the PCI regions" [02/26] ppc: qemu: Update MAINTAINERS for correct email address [03/26] common: fdt_support: Support special case of PCI address in fdt_read_prop() [04/26] ppc: qemu: Support non-identity PCI bus address [05/26] ppc: qemu: Fix CONFIG_SYS_PCI_MAP_END [06/26] ppc: mpc85xx: Wrap LAW related codes with CONFIG_FSL_LAW [07/26] ppc: qemu: Drop init_laws() and print_laws() [08/26] ppc: qemu: Drop board_early_init_f() [09/26] ppc: qemu: Enable OF_CONTROL [10/26] ppc: qemu: Enable driver model [11/26] include: Remove extern from addr_map.h [12/26] lib: addr_map: Move address_map[] type to the header file [13/26] cmd: Add a command to display the address map [14/26] lib: kconfig: Mention CONFIG_ADDR_MAP limitation in the help [15/26] ppc: io.h: Use addrmap_ translation APIs only in post-relocation phase [16/26] common: Move initr_addr_map() to a bit earlier [17/26] ppc: qemu: Switch over to use DM serial [18/26] pci: mpc85xx: Wrap LAW programming with CONFIG_FSL_LAW [19/26] pci: mpc85xx: Support controller register physical address beyond 32-bit [20/26] pci: mpc85xx: Support 64-bit bus and cpu address [21/26] ppc: qemu: Switch over to use DM ETH and PCI [22/26] ppc: qemu: Drop CONFIG_OF_BOARD_SETUP [23/26] cmd: Fix virtio command dependency [24/26] ppc: qemu: Enable VirtIO NET support [25/26] ppc: qemu: Move board directory from board/freescale to board/emulation [26/26] doc: Add a reST document for qemu-ppce500

Message ID

1612710687-56493-21-git-send-email-bmeng.cn@gmail.com

State

Superseded

Delegated to:

Priyanka Jain

Headers

From: Bin Meng <bmeng.cn@gmail.com>
To: Simon Glass <sjg@chromium.org>, Alexander Graf <agraf@csgraf.de>,
 Priyanka Jain <priyanka.jain@nxp.com>
Cc: Tom Rini <trini@konsulko.com>, U-Boot Mailing List <u-boot@lists.denx.de>,
 Heiko Schocher <hs@denx.de>
Subject: [PATCH 20/26] pci: mpc85xx: Support 64-bit bus and cpu address
Date: Sun,  7 Feb 2021 23:11:20 +0800
Message-Id: <1612710687-56493-21-git-send-email-bmeng.cn@gmail.com>
In-Reply-To: <1612710687-56493-1-git-send-email-bmeng.cn@gmail.com>
References: <1612710687-56493-1-git-send-email-bmeng.cn@gmail.com>
Precedence: list
Errors-To: u-boot-bounces@lists.denx.de
Sender: "U-Boot" <u-boot-bounces@lists.denx.de>

Series

ppc: qemu: Convert qemu-ppce500 to driver model | expand

Commit Message

Bin Meng Feb. 7, 2021, 3:11 p.m. UTC

At present the driver only supports 32-bit bus and cpu address.
The controller's outbound registers/fields for extended address
are not programmed. Let's program them to support 64-bit bus and
cpu address.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 drivers/pci/pci_mpc85xx.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/drivers/pci/pci_mpc85xx.c b/drivers/pci/pci_mpc85xx.c
index f0d469a..574cb78 100644
--- a/drivers/pci/pci_mpc85xx.c
+++ b/drivers/pci/pci_mpc85xx.c
@@ -93,18 +93,18 @@  static int mpc85xx_pci_dm_probe(struct udevice *dev)
 
 	pcix = priv->cfg_addr;
 	/* BAR 1: memory */
-	out_be32(&pcix->potar1, (mem->bus_start >> 12) & 0x000fffff);
-	out_be32(&pcix->potear1, 0);
-	out_be32(&pcix->powbar1, (mem->phys_start >> 12) & 0x000fffff);
-	out_be32(&pcix->powbear1, 0);
+	out_be32(&pcix->potar1, mem->bus_start >> 12);
+	out_be32(&pcix->potear1, (u64)mem->bus_start >> 44);
+	out_be32(&pcix->powbar1, mem->phys_start >> 12);
+	out_be32(&pcix->powbear1, (u64)mem->phys_start >> 44);
 	out_be32(&pcix->powar1, (POWAR_EN | POWAR_MEM_READ |
 		 POWAR_MEM_WRITE | (__ilog2(mem->size) - 1)));
 
 	/* BAR 1: IO */
-	out_be32(&pcix->potar2, (io->bus_start >> 12) & 0x000fffff);
-	out_be32(&pcix->potear2, 0);
-	out_be32(&pcix->powbar2, (io->phys_start >> 12) & 0x000fffff);
-	out_be32(&pcix->powbear2, 0);
+	out_be32(&pcix->potar2, io->bus_start >> 12);
+	out_be32(&pcix->potear2, (u64)io->bus_start >> 44);
+	out_be32(&pcix->powbar2, io->phys_start >> 12);
+	out_be32(&pcix->powbear2, (u64)io->phys_start >> 44);
 	out_be32(&pcix->powar2, (POWAR_EN | POWAR_IO_READ |
 		 POWAR_IO_WRITE | (__ilog2(io->size) - 1)));

[20/26] pci: mpc85xx: Support 64-bit bus and cpu address

Commit Message

Patch