diff mbox series

[5/7] spi: zynqmp_gqspi: Fix write issues in single mode

Message ID 1610973148-22465-6-git-send-email-ashok.reddy.soma@xilinx.com
State Deferred
Delegated to: Tom Rini
Headers show
Series zynqmp_gqspi driver updates | expand

Commit Message

Ashok Reddy Soma Jan. 18, 2021, 12:32 p.m. UTC 
Add dummy write to genfifo register in chipselect.

Enable manual start in zynqmp_qspi_fill_gen_fifo().

Also enable GQSPI_IXR_GFNFULL_MASK and check for it instead of
GQSPI_IXR_GFEMTY_MASK.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
---

 drivers/spi/zynqmp_gqspi.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

--
2.17.1

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diff mbox series

Patch

diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 136c20f09e..f50a7304ea 100644
--- a/drivers/spi/zynqmp_gqspi.c
+++ b/drivers/spi/zynqmp_gqspi.c
@@ -239,10 +239,21 @@  static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
                                      u32 gqspi_fifo_reg)
 {
        struct zynqmp_qspi_regs *regs = priv->regs;
+       u32 config_reg, ier;
        int ret = 0;

+       config_reg = readl(&regs->confr);
+       /* Manual start if needed */
+       config_reg |= GQSPI_STRT_GEN_FIFO;
+       writel(config_reg, &regs->confr);
+
+       /* Enable interrupts */
+       ier = readl(&regs->ier);
+       ier |= GQSPI_IXR_GFNFULL_MASK;
+       writel(ier, &regs->ier);
+
        /* Wait until the fifo is not full to write the new command */
-       ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFEMTY_MASK, 1,
+       ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFNFULL_MASK, 1,
                                GQSPI_TIMEOUT, 1);
        if (ret)
                printf("%s Timeout\n", __func__);
@@ -265,6 +276,9 @@  static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)

        debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);

+       /* Dummy generic FIFO entry */
+       zynqmp_qspi_fill_gen_fifo(priv, 0);
+
        zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
 }