@@ -45,6 +45,18 @@
};
};
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins_default>;
@@ -90,6 +90,42 @@
reg = <0x10200a80 0x50>;
};
+ i2c0: i2c@11007000 {
+ compatible = "mediatek,mt8512-i2c";
+ reg = <0x11007000 0x1000>,
+ <0x11000080 0x80>;
+ clocks = <&infracfg CLK_INFRA_I2C0_AXI>,
+ <&infracfg CLK_INFRA_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@10019000 {
+ compatible = "mediatek,mt8512-i2c";
+ reg = <0x10019000 0x1000>,
+ <0x11000100 0x80>;
+ clocks = <&infracfg CLK_INFRA_I2C1_AXI>,
+ <&infracfg CLK_INFRA_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@1001e000 {
+ compatible = "mediatek,mt8512-i2c";
+ reg = <0x1001e000 0x1000>,
+ <0x11000180 0x80>;
+ clocks = <&infracfg CLK_INFRA_I2C1_AXI>,
+ <&infracfg CLK_INFRA_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
uart0: serial@11002000 {
compatible = "mediatek,hsuart";
reg = <0x11002000 0x1000>;
@@ -112,4 +148,4 @@
status = "disabled";
};
-};
\ No newline at end of file
+};