diff mbox series

[1/2] ram: sifive: Check return value on clk_enable()

Message ID 1600157107-57175-1-git-send-email-bmeng.cn@gmail.com
State Accepted
Commit f8c9660bfe17100a27ca4cf28f957a25cb420255
Delegated to: Andes
Headers show
Series [1/2] ram: sifive: Check return value on clk_enable() | expand

Commit Message

Bin Meng Sept. 15, 2020, 8:05 a.m. UTC
From: Bin Meng <bin.meng@windriver.com>

The return value should be checked otherwise it's useless to
assign the return value to 'ret'.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
---

 drivers/ram/sifive/fu540_ddr.c | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Bin Meng Sept. 25, 2020, 6:31 a.m. UTC | #1
On Tue, Sep 15, 2020 at 4:05 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> From: Bin Meng <bin.meng@windriver.com>
>
> The return value should be checked otherwise it's useless to
> assign the return value to 'ret'.
>
> Signed-off-by: Bin Meng <bin.meng@windriver.com>
> ---
>
>  drivers/ram/sifive/fu540_ddr.c | 5 +++++
>  1 file changed, 5 insertions(+)
>

ping?
Rick Chen Sept. 25, 2020, 6:50 a.m. UTC | #2
> From: Bin Meng [mailto:bmeng.cn@gmail.com]
> Sent: Friday, September 25, 2020 2:31 PM
> To: Rick Jian-Zhi Chen(陳建志); Pragnesh Patel; U-Boot Mailing List
> Cc: Bin Meng
> Subject: Re: [PATCH 1/2] ram: sifive: Check return value on clk_enable()
>
> On Tue, Sep 15, 2020 at 4:05 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > From: Bin Meng <bin.meng@windriver.com>
> >
> > The return value should be checked otherwise it's useless to
> > assign the return value to 'ret'.
> >
> > Signed-off-by: Bin Meng <bin.meng@windriver.com>
> > ---
> >
> >  drivers/ram/sifive/fu540_ddr.c | 5 +++++
> >  1 file changed, 5 insertions(+)
> >
>
> ping?

Applied to u-boot-riscv/master!

Thanks,
Rick
diff mbox series

Patch

diff --git a/drivers/ram/sifive/fu540_ddr.c b/drivers/ram/sifive/fu540_ddr.c
index 5ff8869..f5b2873 100644
--- a/drivers/ram/sifive/fu540_ddr.c
+++ b/drivers/ram/sifive/fu540_ddr.c
@@ -369,6 +369,11 @@  static int fu540_ddr_probe(struct udevice *dev)
 	}
 
 	ret = clk_enable(&priv->ddr_clk);
+	if (ret < 0) {
+		debug("Could not enable DDR clock\n");
+		return ret;
+	}
+
 	priv->ctl = regmap_get_range(map, 0);
 	priv->phy = regmap_get_range(map, 1);
 	priv->physical_filter_ctrl = regmap_get_range(map, 2);