| Message ID | 1594370308-30957-3-git-send-email-sagar.kadam@sifive.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | add DM based reset driver for SiFive SoC's | expand |
>-----Original Message----- >From: Sagar Kadam <sagar.kadam@sifive.com> >Sent: 10 July 2020 14:08 >To: u-boot@lists.denx.de >Cc: rick@andestech.com; Paul Walmsley ( Sifive) ><paul.walmsley@sifive.com>; palmer@dabbelt.com; anup.patel@wdc.com; >atish.patra@wdc.com; lukma@denx.de; Pragnesh Patel ><pragnesh.patel@sifive.com>; bin.meng@windriver.com; >jagan@amarulasolutions.com; sjg@chromium.org; twoerner@gmail.com; >abrodkin@synopsys.com; Eugeniy.Paltsev@synopsys.com; patrick@blueri.se; >weijie.gao@mediatek.com; festevam@gmail.com; Sagar Kadam ><sagar.kadam@sifive.com> >Subject: [PATCH v3 2/5] fu540: prci: use common reset indexes defined in >binding header > >Indexes of reset signals available in PRCI driver are also defined in include/dt- >bindings/reset/sifive-fu540-prci.h. >So use those instead of defining new ones again within the fu540-prci driver. > >Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> >--- > drivers/clk/sifive/fu540-prci.c | 17 +++++++---------- > 1 file changed, 7 insertions(+), 10 deletions(-) > Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com>
On Fri, Jul 10, 2020 at 4:39 PM Sagar Shrikant Kadam <sagar.kadam@sifive.com> wrote: > > Indexes of reset signals available in PRCI driver are also > defined in include/dt-bindings/reset/sifive-fu540-prci.h. > So use those instead of defining new ones again within the > fu540-prci driver. > > Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> > --- > drivers/clk/sifive/fu540-prci.c | 17 +++++++---------- > 1 file changed, 7 insertions(+), 10 deletions(-) > Reviewed-by: Bin Meng <bin.meng@windriver.com>
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index fe6e0d4..00c31fc 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -41,6 +41,7 @@ #include <linux/math64.h> #include <linux/clk/analogbits-wrpll-cln28hpc.h> #include <dt-bindings/clock/sifive-fu540-prci.h> +#include <dt-bindings/reset/sifive-fu540-prci.h> /* * EXPECTED_CLK_PARENT_COUNT: how many parent clocks this driver expects: @@ -131,21 +132,17 @@ /* DEVICESRESETREG */ #define PRCI_DEVICESRESETREG_OFFSET 0x28 -#define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT 0 + #define PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_MASK \ - (0x1 << PRCI_DEVICESRESETREG_DDR_CTRL_RST_N_SHIFT) -#define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT 1 + (0x1 << PRCI_RST_DDR_CTRL_N) #define PRCI_DEVICESRESETREG_DDR_AXI_RST_N_MASK \ - (0x1 << PRCI_DEVICESRESETREG_DDR_AXI_RST_N_SHIFT) -#define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT 2 + (0x1 << PRCI_RST_DDR_AXI_N) #define PRCI_DEVICESRESETREG_DDR_AHB_RST_N_MASK \ - (0x1 << PRCI_DEVICESRESETREG_DDR_AHB_RST_N_SHIFT) -#define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT 3 + (0x1 << PRCI_RST_DDR_AHB_N) #define PRCI_DEVICESRESETREG_DDR_PHY_RST_N_MASK \ - (0x1 << PRCI_DEVICESRESETREG_DDR_PHY_RST_N_SHIFT) -#define PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT 5 + (0x1 << PRCI_RST_DDR_PHY_N) #define PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK \ - (0x1 << PRCI_DEVICESRESETREG_GEMGXL_RST_N_SHIFT) + (0x1 << PRCI_RST_GEMGXL_N) /* CLKMUXSTATUSREG */ #define PRCI_CLKMUXSTATUSREG_OFFSET 0x2c
Indexes of reset signals available in PRCI driver are also defined in include/dt-bindings/reset/sifive-fu540-prci.h. So use those instead of defining new ones again within the fu540-prci driver. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> --- drivers/clk/sifive/fu540-prci.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-)