@@ -1677,6 +1677,10 @@ config TARGET_PRESIDIO_ASIC
bool "Support Cortina Presidio ASIC Platform"
select ARM64
+config TARGET_VENUS
+ bool "Support Cortina Venus Platform"
+ select ARM64
+
endchoice
config ARCH_SUPPORT_TFABOOT
@@ -1826,6 +1830,7 @@ source "board/armadeus/apf27/Kconfig"
source "board/armltd/vexpress/Kconfig"
source "board/armltd/vexpress64/Kconfig"
source "board/cortina/presidio-asic/Kconfig"
+source "board/cortina/venus/Kconfig"
source "board/broadcom/bcm23550_w1d/Kconfig"
source "board/broadcom/bcm28155_ap/Kconfig"
source "board/broadcom/bcm963158/Kconfig"
@@ -925,6 +925,7 @@ dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb
dtb-$(CONFIG_TARGET_DURIAN) += phytium-durian.dtb
dtb-$(CONFIG_TARGET_PRESIDIO_ASIC) += ca-presidio-engboard.dtb
+dtb-$(CONFIG_TARGET_VENUS) += ca-venus-engboard.dtb
targets += $(dtb-y)
new file mode 100644
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020, Cortina Access Inc.
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <1>;
+
+ mmc0: mmc@0xf4400000 {
+ compatible = "snps,dw-cortina";
+ reg = <0x0 0xf4400000 0x1000>;
+ bus-width = <4>;
+ io_ds = <0x77>;
+ fifo-mode;
+ sd_dll_ctrl = <0xf43200e8>;
+ io_drv_ctrl = <0xf432004c>;
+ };
+
+ gpio0: gpio-controller@0xf43292c0 {
+ compatible = "cortina,ca-gpio";
+ reg = <0x0 0xf43292c0 0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "okay";
+ };
+ gpio1: gpio-controller@0xf43292e4 {
+ compatible = "cortina,ca-gpio";
+ reg = <0x0 0xf43292e4 0x24>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ watchdog: watchdog@0xf432901c {
+ compatible = "cortina,ca-wdt";
+ reg = <0x0 0xf432901c 0x34>,
+ <0x0 0xf432004c 0x04>;
+ status = "okay";
+ };
+
+ uart0: serial@0xf4329188 {
+ u-boot,dm-pre-reloc;
+ compatible = "cortina,ca-uart";
+ reg = <0x0 0xf4329188 0x30>;
+ status = "okay";
+ };
+
+ i2c: i2c@f4329120 {
+ compatible = "cortina,ca-i2c";
+ reg = <0x0 0xf4329160 0x28>;
+ clock-frequency = <400000>;
+ };
+
+ sflash: sflash-controller@f4324000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "cortina,ca-sflash";
+ reg = <0x0 0xf4324000 0x50>;
+ reg-names = "sflash-regs";
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ spi-rx-bus-width = <1>;
+ spi-max-frequency = <108000000>;
+ };
+ };
+};
new file mode 100644
@@ -0,0 +1,16 @@
+if TARGET_VENUS
+config BIT64
+ bool
+ default y
+
+config SYS_BOARD
+ default "venus"
+
+config SYS_VENDOR
+ default "cortina"
+
+config SYS_CONFIG_NAME
+ default "venus"
+
+source "board/cortina/common/Kconfig"
+endif
new file mode 100644
@@ -0,0 +1,6 @@
+Cortina Venus ASIC Engineering BOARD
+M: Alex Nemirovsky <alex.nemirovsky@cortina-access.com>
+S: Supported
+F: board/cortina/venus/
+F: include/configs/venus.h
+F: configs/cortina_venus*defconfig
new file mode 100644
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2020 Cortina-Access.Inc.
+#
+#
+
+obj-y := venus.o
+obj-y += lowlevel_init.o
new file mode 100644
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Cortina-Access
+ *
+ */
+
+#include <asm-offsets.h>
+#include <config.h>
+#include <linux/linkage.h>
+#include <asm/macro.h>
+#include <asm/armv8/mmu.h>
+
+ .globl lowlevel_init
+lowlevel_init:
+ mov x29, lr /* Save LR */
+
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+ branch_if_slave x0, 1f
+ ldr x0, =GICD_BASE
+1:
+#if defined(CONFIG_GICV3)
+ ldr x0, =GICR_BASE
+#elif defined(CONFIG_GICV2)
+ ldr x0, =GICD_BASE
+ ldr x1, =GICC_BASE
+ bl gic_init_secure_percpu
+#endif
+#endif
+
+#ifdef CONFIG_ARMV8_MULTIENTRY
+ branch_if_master x0, x1, 2f
+
+ /*
+ * Slave should wait for master clearing spin table.
+ * This sync prevent salves observing incorrect
+ * value of spin table and jumping to wrong place.
+ */
+#if defined(CONFIG_GICV2) || defined(CONFIG_GICV3)
+#ifdef CONFIG_GICV2
+ ldr x0, =GICC_BASE
+#endif
+ bl gic_wait_for_interrupt
+#endif
+
+ /*
+ * All slaves will enter EL2 and optionally EL1.
+ */
+ adr x4, lowlevel_in_el2
+ ldr x5, =ES_TO_AARCH64
+ bl armv8_switch_to_el2
+
+lowlevel_in_el2:
+#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+ adr x4, lowlevel_in_el1
+ ldr x5, =ES_TO_AARCH64
+ bl armv8_switch_to_el1
+
+lowlevel_in_el1:
+#endif
+
+#endif /* CONFIG_ARMV8_MULTIENTRY */
+
+2:
+ mov lr, x29 /* Restore LR */
+ ret
new file mode 100644
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 - Cortina Access Inc.
+ *
+ */
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <asm/io.h>
+#include <linux/compiler.h>
+#include <configs/venus.h>
+#include <linux/psci.h>
+#include <asm/psci.h>
+#include <cpu_func.h>
+#include <asm/armv8/mmu.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define CA_PERIPH_BASE 0xE0000000UL
+#define CA_PERIPH_SIZE 0x20000000UL
+#define CA_GLOBAL_BASE 0xf4320000
+#define CA_GLOBAL_JTAG_ID 0xf4320000
+#define CA_GLOBAL_BLOCK_RESET 0xf4320028
+#define CA_GLOBAL_BLOCK_RESET_RESET_DMA BIT(16)
+#define CA_DMA_SEC_SSP_BAUDRATE_CTRL 0xf7001b94
+#define CA_DMA_SEC_SSP_ID 0xf7001b80
+#define CA_DDR_ALIAS_BASE 0x100000000
+#define VENUS_TPS56921_HW_ADDR 0x37
+
+int print_cpuinfo(void)
+{
+ printf("CPU: Cortina Venus\n");
+ return 0;
+}
+
+static struct mm_region venus_mem_map[] = {
+ {
+ .virt = DDR_BASE,
+ .phys = DDR_BASE,
+ .size = PHYS_SDRAM_1_SIZE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_OUTER_SHARE
+ },
+ {
+ .virt = CA_PERIPH_BASE,
+ .phys = CA_PERIPH_BASE,
+ .size = CA_PERIPH_SIZE,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE
+ },
+ {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = venus_mem_map;
+
+static noinline int invoke_psci_fn_smc(u64 function_id, u64 arg0, u64 arg1,
+ u64 arg2)
+{
+ asm volatile("mov x0, %0\n"
+ "mov x1, %1\n"
+ "mov x2, %2\n"
+ "mov x3, %3\n"
+ "smc #0\n"
+ : "+r" (function_id)
+ : "r" (arg0), "r" (arg1), "r" (arg2)
+ );
+
+ return function_id;
+}
+
+int board_early_init_r(void)
+{
+ dcache_disable();
+ return 0;
+}
+
+int board_init(void)
+{
+ /* Enable timer */
+ writel(1, CONFIG_SYS_TIMER_BASE);
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ unsigned int ddr_size, i = 0;
+
+ ddr_size = readl(0x111100c);
+
+ /* DRAM size should be filled by DDR init code(BL2).\
+ * Hard code ddr_size here if no BL2!
+ */
+
+ if (ddr_size > 240) {
+ /* tail of 256M are reserved for secure firmware(BL31/BL32) */
+ gd->bd->bi_dram[i].start = PHYS_SDRAM_1;
+ gd->bd->bi_dram[i].size = 240 * 0x100000;
+ gd->ram_size = gd->bd->bi_dram[i].size;
+ i++;
+ }
+
+ /* segment #2 start from offset of 256M */
+ if (ddr_size > 256) {
+ if (ddr_size <= 2048)
+ gd->bd->bi_dram[i].size = (ddr_size - 256) * 0x100000;
+ else
+ gd->bd->bi_dram[i].size = (2048 - 256) * 0x100000;
+
+ gd->ram_size += gd->bd->bi_dram[i].size;
+ i++;
+ }
+
+ /* Segment #3:
+ * Tail of base address 0 are for PCI and IO port.
+ * So we must use DDR alias base to add DDR bank.
+ */
+ if (ddr_size > 2048) {
+ gd->bd->bi_dram[i].start = CA_DDR_ALIAS_BASE + SZ_2G;
+ gd->bd->bi_dram[i].size = (ddr_size - 2048) * 0x100000;
+ gd->ram_size += gd->bd->bi_dram[i].size;
+ i++;
+ }
+
+ for ( ; i < CONFIG_NR_DRAM_BANKS; ++i) {
+ gd->bd->bi_dram[i].start = 0;
+ gd->bd->bi_dram[i].size = 0;
+ }
+
+ return 0;
+}
+
+int dram_init_banksize(void)
+{
+ return dram_init();
+}
+
+void reset_cpu(ulong addr)
+{
+ invoke_psci_fn_smc(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0);
+}
+
+#ifdef CONFIG_LAST_STAGE_INIT
+int last_stage_init(void)
+{
+ u32 val;
+
+ val = readl(CA_GLOBAL_BLOCK_RESET);
+ val &= ~CA_GLOBAL_BLOCK_RESET_RESET_DMA;
+ writel(val, CA_GLOBAL_BLOCK_RESET);
+
+ /* reduce output pclk ~3.7Hz to save power consumption */
+ writel(0x000000FF, CA_DMA_SEC_SSP_BAUDRATE_CTRL);
+
+ return 0;
+}
+#endif
new file mode 100644
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+# CONFIG_SYS_ARCH_TIMER is not set
+CONFIG_TARGET_VENUS=y
+CONFIG_SYS_TEXT_BASE=0x04000000
+CONFIG_ENV_SIZE=0x20000
+CONFIG_DM_GPIO=y
+CONFIG_NR_DRAM_BANKS=4
+CONFIG_IDENT_STRING="Venus-SoC"
+CONFIG_SHOW_BOOT_PROGRESS=y
+CONFIG_BOOTDELAY=3
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="earlycon=serial,0xf4329188 console=ttyS0,115200 root=/dev/ram0"
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SYS_PROMPT="VENUS#"
+CONFIG_CMD_WDT=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_SMC=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIVE=y
+CONFIG_DEFAULT_DEVICE_TREE="ca-venus-engboard"
+# CONFIG_NET is not set
+CONFIG_DM=y
+CONFIG_CORTINA_GPIO=y
+# CONFIG_MMC is not set
+CONFIG_DM_SERIAL=y
+CONFIG_CORTINA_UART=y
+CONFIG_WDT=y
+CONFIG_WDT_CORTINA=y
new file mode 100644
@@ -0,0 +1,74 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Cortina Access Inc.
+ *
+ * Configuration for Cortina-Access Venus board.
+ */
+
+#ifndef __VENUS_H
+#define __VENUS_H
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_SUPPORT_RAW_INITRD
+
+#define CONFIG_SYS_INIT_SP_ADDR 0x00100000
+#define CONFIG_SYS_BOOTM_LEN 0x00c00000
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY 25000000
+#define CONFIG_SYS_TIMER_RATE COUNTER_FREQUENCY
+#define CONFIG_SYS_TIMER_COUNTER 0xf4321008
+
+/* note: arch/arm/cpu/armv8/start.S which references GICD_BASE/GICC_BASE
+ * does not yet support DT. Thus define it here.
+ */
+#define CONFIG_GICV3
+#define GICD_BASE 0x4F8000000
+#define GICR_BASE 0x4F8040000
+
+#define CONFIG_SYS_MEMTEST_SCRATCH 0x00100000
+#define CONFIG_SYS_MEMTEST_START 0x05000000
+#define CONFIG_SYS_MEMTEST_END 0x0D000000
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (8 << 20))
+
+#define CONFIG_SYS_TIMER_BASE 0xf4321000
+
+/* Use external clock source */
+#define VENUS_APB_CLK 125000000
+#define CORTINA_PER_IO_FREQ VENUS_APB_CLK
+
+/* Cortina Serial Configuration */
+#define CORTINA_UART_CLOCK (VENUS_APB_CLK)
+#define CORTINA_SERIAL_PORTS {(void *)CONFIG_SYS_SERIAL0, \
+ (void *)CONFIG_SYS_SERIAL1}
+
+#define CONFIG_BAUDRATE 115200
+#define CONFIG_SYS_SERIAL0 PER_UART0_CFG
+#define CONFIG_SYS_SERIAL1 PER_UART1_CFG
+
+/* BOOTP options */
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+/* Miscellaneous configurable options */
+#define CONFIG_SYS_LOAD_ADDR (DDR_BASE + 0x10000000)
+#define CONFIG_LAST_STAGE_INIT
+
+/* SDRAM Bank #1 */
+#define DDR_BASE 0x00000000
+#define PHYS_SDRAM_1 DDR_BASE
+#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2GB */
+
+/* Console I/O Buffer Size */
+#define CONFIG_SYS_CBSIZE 256
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+/* max command args */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS "silent=y\0"
+
+#endif /* __VENUS_H */