diff mbox series

[v3,2/8] clk: stm32mp1: Add a clock entry for RNG1 device

Message ID 1576221267-5948-3-git-send-email-sughosh.ganu@linaro.org
State Superseded, archived
Delegated to: Tom Rini
Headers show
Series Add a random number generator uclass | expand

Commit Message

Sughosh Ganu Dec. 13, 2019, 7:14 a.m. UTC 
Add an entry for allowing clock enablement for the random number
generator peripheral, RNG1.

Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
---
 drivers/clk/clk_stm32mp1.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Patrick DELAUNAY Dec. 16, 2019, 8:55 a.m. UTC | #1 
Hi,

> From: U-Boot <u-boot-bounces@lists.denx.de> On Behalf Of Sughosh Ganu
> Sent: vendredi 13 décembre 2019 08:14
> 
> Add an entry for allowing clock enablement for the random number generator
> peripheral, RNG1.
> 
> Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org>
> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>

Acked-by: Patrick Delaunay <patrick.delaunay@st.com>

Thanks.
diff mbox series

Patch

diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index 3718970..da66bde 100644
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -563,6 +563,7 @@  static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
 	STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 10, GPIOK, _UNKNOWN_SEL),
 
 	STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 0, GPIOZ, _UNKNOWN_SEL),
+	STM32MP1_CLK_SET_CLR(RCC_MP_AHB5ENSETR, 6, RNG1_K, _UNKNOWN_SEL),
 
 	STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 7, ETHCK_K, _ETH_SEL),
 	STM32MP1_CLK_SET_CLR(RCC_MP_AHB6ENSETR, 8, ETHTX, _UNKNOWN_SEL),