From patchwork Thu Jul 18 07:34:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bin Meng X-Patchwork-Id: 1133597 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="euvyQEkS"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45q5yn5kvpz9s00 for ; Thu, 18 Jul 2019 17:55:13 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 713D5C21FDD; Thu, 18 Jul 2019 07:49:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 7FAACC21FD9; Thu, 18 Jul 2019 07:36:25 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C5683C21DF8; Thu, 18 Jul 2019 07:35:16 +0000 (UTC) Received: from mail-pf1-f174.google.com (mail-pf1-f174.google.com [209.85.210.174]) by lists.denx.de (Postfix) with ESMTPS id 5FDAAC21DF8 for ; Thu, 18 Jul 2019 07:35:09 +0000 (UTC) Received: by mail-pf1-f174.google.com with SMTP id t16so12177753pfe.11 for ; Thu, 18 Jul 2019 00:35:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:subject:date:message-id:in-reply-to:references; bh=wJffG4Uabsj+5UCZFp1yt5i96d1hPU+i9ymmioFG+zI=; b=euvyQEkS2sA2Nr5sX825TSiR23/i7evECR8w/0YJhctRbUnMGPNW3+zlksy0VXq6T+ AllttDjJrSmKWuLdjYlLKbrva/bBTXpPIVONgHLqZvSDXhNnsxLmmfVTIQMKOyEPvwPv EtGwkFwKbieiWFg/tGUy6XEO1Yoc8xI+eDZ+V8KAaz6VSpijOwkcqEhx4XqwvJmByuFN GjwsNZ5290NTr65UPGYIjaFgMkyD1b8iIiUMxZwPLpR/H25tQubqaw6N0qArti8MPHfk fiSkka+zVpswIJKwT6T6gC89u5ZiNZznVf2oK98NkyZ84519k+pMEHeX+ROWVZcsys+J 35Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references; bh=wJffG4Uabsj+5UCZFp1yt5i96d1hPU+i9ymmioFG+zI=; b=lOkT6l39I4RofFkGtCV/yg3XLCXg5MdqIB6wNpNlEj8hHA7y4sKGHrOoXmd1e0498y YpmRazcrANAzMeQ4+YOsMs4XQB/RboXyuhOMsP4LZyn1VBl7YrYYAdBme0okqzzvXHtb 8nwik77BxpZnk9kRAdQSfsLMa6RQ5VDygY0metse6X2ZY+JkwcnQxVEl+LlwZGXrw7v3 3JxetsWZ3xNXctQq/5XvLzpg6h+/L/0oJ3O99o8Iop5gS/SfPFmjyn70O4ww7rHKIYNO dBzjFh3vbNAINKt08p2Bf11E4WW1NpbS4rrUTbdj5MeC7K4jQgerZwQCsiMtQM/4Nuj+ E+KA== X-Gm-Message-State: APjAAAWlUil8mpu8goopOEx3pdzAPh9eNPuQlNzXVw73v94kdxv99ySn +vicOGyX5rNhtiZjLnluPHs= X-Google-Smtp-Source: APXvYqycB0aLJKlruTnP+EWn2yZj5kI7FBHvBSjWmRszMNqh2IE7/MK8ef0RXbp5IGmODPKAtB920w== X-Received: by 2002:a17:90a:1ae2:: with SMTP id p89mr46913455pjp.26.1563435303632; Thu, 18 Jul 2019 00:35:03 -0700 (PDT) Received: from localhost.localdomain (unknown-224-80.windriver.com. [147.11.224.80]) by smtp.gmail.com with ESMTPSA id q1sm39859821pfn.178.2019.07.18.00.35.02 (version=TLS1 cipher=AES128-SHA bits=128/128); Thu, 18 Jul 2019 00:35:03 -0700 (PDT) From: Bin Meng To: Tom Rini , Simon Glass , Wolfgang Denk , Heinrich Schuchardt , Mario Six , U-Boot Mailing List Date: Thu, 18 Jul 2019 00:34:05 -0700 Message-Id: <1563435275-22326-21-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 In-Reply-To: <1563435275-22326-1-git-send-email-bmeng.cn@gmail.com> References: <1563435275-22326-1-git-send-email-bmeng.cn@gmail.com> Subject: [U-Boot] [PATCH 20/50] doc: board: Add Intel Crown Bay board doc X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This extracts Intel Crown Bay board specific information from README.x86, converts plain text documentation to reST format and adds it to Sphinx TOC tree. No essential content change. Signed-off-by: Bin Meng --- doc/README.x86 | 37 ------------------------------------- doc/board/index.rst | 2 ++ doc/board/intel/crownbay.rst | 43 +++++++++++++++++++++++++++++++++++++++++++ doc/board/intel/index.rst | 9 +++++++++ 4 files changed, 54 insertions(+), 37 deletions(-) create mode 100644 doc/board/intel/crownbay.rst create mode 100644 doc/board/intel/index.rst diff --git a/doc/README.x86 b/doc/README.x86 index 8e0a3f3..8077ff3 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -203,43 +203,6 @@ Flash map for samus / broadwell: --- -Intel Crown Bay specific instructions for bare mode: - -U-Boot support of Intel Crown Bay board [4] relies on a binary blob called -Firmware Support Package [5] to perform all the necessary initialization steps -as documented in the BIOS Writer Guide, including initialization of the CPU, -memory controller, chipset and certain bus interfaces. - -Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, -install it on your host and locate the FSP binary blob. Note this platform -also requires a Chipset Micro Code (CMC) state machine binary to be present in -the SPI flash where u-boot.rom resides, and this CMC binary blob can be found -in this FSP package too. - -* ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd -* ./Microcode/C0_22211.BIN - -Rename the first one to fsp.bin and second one to cmc.bin and put them in the -board directory. - -Note the FSP release version 001 has a bug which could cause random endless -loop during the FspInit call. This bug was published by Intel although Intel -did not describe any details. We need manually apply the patch to the FSP -binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP -binary, change the following five bytes values from orginally E8 42 FF FF FF -to B8 00 80 0B 00. - -As for the video ROM, you need manually extract it from the Intel provided -BIOS for Crown Bay here [6], using the AMI MMTool [7]. Check PCI option ROM -ID 8086:4108, extract and save it as vga.bin in the board directory. - -Now you can build U-Boot and obtain u-boot.rom - -$ make crownbay_defconfig -$ make all - ---- - Intel Cougar Canyon 2 specific instructions for bare mode: This uses Intel FSP for 3rd generation Intel Core and Intel Celeron processors diff --git a/doc/board/index.rst b/doc/board/index.rst index b47f672..99b5d2f 100644 --- a/doc/board/index.rst +++ b/doc/board/index.rst @@ -5,3 +5,5 @@ Board-specific doc .. toctree:: :maxdepth: 2 + + intel/index diff --git a/doc/board/intel/crownbay.rst b/doc/board/intel/crownbay.rst new file mode 100644 index 0000000..4fcf981 --- /dev/null +++ b/doc/board/intel/crownbay.rst @@ -0,0 +1,43 @@ +.. SPDX-License-Identifier: GPL-2.0+ +.. sectionauthor:: Bin Meng + +Crown Bay CRB +============= + +U-Boot support of Intel `Crown Bay`_ board relies on a binary blob called +Firmware Support Package (`FSP`_) to perform all the necessary initialization +steps as documented in the BIOS Writer Guide, including initialization of the +CPU, memory controller, chipset and certain bus interfaces. + +Download the Intel FSP for Atom E6xx series and Platform Controller Hub EG20T, +install it on your host and locate the FSP binary blob. Note this platform +also requires a Chipset Micro Code (CMC) state machine binary to be present in +the SPI flash where u-boot.rom resides, and this CMC binary blob can be found +in this FSP package too. + + * ./FSP/QUEENSBAY_FSP_GOLD_001_20-DECEMBER-2013.fd + * ./Microcode/C0_22211.BIN + +Rename the first one to fsp.bin and second one to cmc.bin and put them in the +board directory. + +Note the FSP release version 001 has a bug which could cause random endless +loop during the FspInit call. This bug was published by Intel although Intel +did not describe any details. We need manually apply the patch to the FSP +binary using any hex editor (eg: bvi). Go to the offset 0x1fcd8 of the FSP +binary, change the following five bytes values from orginally E8 42 FF FF FF +to B8 00 80 0B 00. + +As for the video ROM, you need manually extract it from the Intel provided +BIOS for Crown Bay `here`_, using the AMI `MMTool`_. Check PCI option +ROM ID 8086:4108, extract and save it as vga.bin in the board directory. + +Now you can build U-Boot and obtain u-boot.rom:: + + $ make crownbay_defconfig + $ make all + +.. _`Crown Bay`: http://www.intel.com/content/www/us/en/embedded/design-tools/evaluation-platforms/atom-e660-eg20t-development-kit.html +.. _`FSP`: http://www.intel.com/fsp +.. _`here`: http://www.intel.com/content/www/us/en/secure/intelligent-systems/privileged/e6xx-35-b1-cmc22211.html +.. _`MMTool`: http://www.ami.com/products/bios-uefi-tools-and-utilities/bios-uefi-utilities/ diff --git a/doc/board/intel/index.rst b/doc/board/intel/index.rst new file mode 100644 index 0000000..93b8ba2 --- /dev/null +++ b/doc/board/intel/index.rst @@ -0,0 +1,9 @@ +.. SPDX-License-Identifier: GPL-2.0+ + +Intel +===== + +.. toctree:: + :maxdepth: 2 + + crownbay