From patchwork Tue Mar 12 11:24:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Meenakshi Aggarwal X-Patchwork-Id: 1055076 X-Patchwork-Delegate: prabhakar@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 44JP1J4fLwz9s4V for ; Tue, 12 Mar 2019 16:39:30 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 6F014C21F29; Tue, 12 Mar 2019 05:39:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: ** X-Spam-Status: No, score=2.4 required=5.0 tests=DATE_IN_FUTURE_03_06, RCVD_IN_DNSWL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4FBB1C21C2F; Tue, 12 Mar 2019 05:39:20 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8CC6FC21BE5; Tue, 12 Mar 2019 05:39:18 +0000 (UTC) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lists.denx.de (Postfix) with ESMTPS id 2800FC21BE5 for ; Tue, 12 Mar 2019 05:39:18 +0000 (UTC) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6CC201A0038; Tue, 12 Mar 2019 06:39:17 +0100 (CET) Received: from inv0113.in-blr01.nxp.com (inv0113.in-blr01.nxp.com [165.114.116.118]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 2AF111A0005; Tue, 12 Mar 2019 06:39:17 +0100 (CET) Received: from uefi-OptiPlex-790.ap.freescale.net (uefi-OptiPlex-790.ap.freescale.net [10.232.132.78]) by inv0113.in-blr01.nxp.com (Postfix) with ESMTP id 4D86432D; Tue, 12 Mar 2019 11:09:16 +0530 (IST) From: Meenakshi Aggarwal To: u-boot@lists.denx.de Date: Tue, 12 Mar 2019 16:54:32 +0530 Message-Id: <1552389872-6420-1-git-send-email-meenakshi.aggarwal@nxp.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1552319051-5392-1-git-send-email-meenakshi.aggarwal@nxp.com> References: <1552319051-5392-1-git-send-email-meenakshi.aggarwal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [U-Boot] [PATCH v2] MC : Report extra reserved memory to Linux X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" For MC, 512 MB DDR is reserved because of MC's alignment requirement. But for MC binaries needing 128MB or 256MB DDR memory, rest of the memory is a waste. So reporting this extra memory to Linux through dtb memory fixup. Signed-off-by: Meenakshi Aggarwal --- board/freescale/lx2160a/lx2160a.c | 28 +++++++++++++++++++++++++++- drivers/net/fsl-mc/mc.c | 13 +++++++++++++ include/fsl-mc/fsl_mc.h | 1 + 3 files changed, 41 insertions(+), 1 deletion(-) diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index ad72eed..b763f6d 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -532,8 +532,15 @@ void board_quiesce_devices(void) int ft_board_setup(void *blob, bd_t *bd) { int i; + bool mc_memory_bank = false; + +#ifdef CONFIG_FSL_MC_ENET + u64 base[CONFIG_NR_DRAM_BANKS + 1]; + u64 size[CONFIG_NR_DRAM_BANKS + 1]; +#else u64 base[CONFIG_NR_DRAM_BANKS]; u64 size[CONFIG_NR_DRAM_BANKS]; +#endif ft_cpu_setup(blob, bd); @@ -556,7 +563,26 @@ int ft_board_setup(void *blob, bd_t *bd) size[2] = gd->arch.resv_ram - base[2]; #endif - fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); +#ifdef CONFIG_FSL_MC_ENET + fdt_fixup_mc_ddr(&base[3], &size[3]); + + if (base[3] != 0) { + for (i = 0; i <= CONFIG_NR_DRAM_BANKS; i++) { + if (base[i] == 0 && size[i] == 0) { + base[i] = base[3]; + size[i] = size[3]; + break; + } + } + if (i == CONFIG_NR_DRAM_BANKS) + mc_memory_bank = true; + } +#endif + if (mc_memory_bank) + fdt_fixup_memory_banks( + blob, base, size, CONFIG_NR_DRAM_BANKS + 1); + else + fdt_fixup_memory_banks(blob, base, size, CONFIG_NR_DRAM_BANKS); #ifdef CONFIG_USB fsl_fdt_fixup_dr_usb(blob, bd); diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c index dddc9cc..d7a2e8f 100644 --- a/drivers/net/fsl-mc/mc.c +++ b/drivers/net/fsl-mc/mc.c @@ -285,6 +285,19 @@ static int mc_fixup_dpl_mac_addr(void *blob, int dpmac_id, MC_FIXUP_DPL); } +void fdt_fixup_mc_ddr(u64 *base, u64 *size) +{ + u64 mc_size = mc_get_dram_block_size(); + + if (mc_size < MC_DRAM_BLOCK_DEFAULT_SIZE) { + *base = mc_get_dram_addr() + mc_size; + *size = MC_DRAM_BLOCK_DEFAULT_SIZE - mc_size; + } else { + *base = 0; + *size = 0; + } +} + void fdt_fsl_mc_fixup_iommu_map_entry(void *blob) { u32 *prop; diff --git a/include/fsl-mc/fsl_mc.h b/include/fsl-mc/fsl_mc.h index aef40d3..492a714 100644 --- a/include/fsl-mc/fsl_mc.h +++ b/include/fsl-mc/fsl_mc.h @@ -54,6 +54,7 @@ struct mc_ccsr_registers { void fdt_fsl_mc_fixup_iommu_map_entry(void *blob); int get_mc_boot_status(void); int get_dpl_apply_status(void); +void fdt_fixup_mc_ddr(u64 *base, u64 *size); #ifdef CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET int get_aiop_apply_status(void); #endif