| Message ID | 1548850026-31746-3-git-send-email-patrick.delaunay@st.com |
|---|---|
| State | Accepted |
| Commit | d661f61847696dc5ac54b397908f886bd3583484 |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | stm32mp1: update clock driver | expand |
On Wed, Jan 30, 2019 at 01:07:01PM +0100, Patrick Delaunay wrote: > Add support for enable/disable of IPCC clock using AHB3 registers > > Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Applied to u-boot/master, thanks!
diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index e3ea29a..e1477a1 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -538,6 +538,7 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = { STM32MP1_CLK_SET_CLR(RCC_MP_AHB2ENSETR, 16, SDMMC3_K, _SDMMC3_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 11, HSEM, _UNKNOWN_SEL), + STM32MP1_CLK_SET_CLR(RCC_MP_AHB3ENSETR, 12, IPCC, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 0, GPIOA, _UNKNOWN_SEL), STM32MP1_CLK_SET_CLR(RCC_MP_AHB4ENSETR, 1, GPIOB, _UNKNOWN_SEL),
Add support for enable/disable of IPCC clock using AHB3 registers Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> --- drivers/clk/clk_stm32mp1.c | 1 + 1 file changed, 1 insertion(+)