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[U-Boot,RFC,5/8] arm: actions: add S700 SoC device tree

Message ID 1546521983-19385-6-git-send-email-amittomer25@gmail.com
State RFC
Delegated to: Tom Rini
Headers show
Series Actions S700 SoC support | expand

Commit Message

Amit Tomer Jan. 3, 2019, 1:26 p.m. UTC 
This patch adds .dtsi file(sync with Linux 4.20) and required binding
for S700 SoC that is a 64-bit Quad-core ARM Cortex-A53 cores.

Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
---
 arch/arm/dts/s700.dtsi                       | 193 +++++++++++++++++++++++++++
 include/dt-bindings/clock/actions,s700-cmu.h | 118 ++++++++++++++++
 2 files changed, 311 insertions(+)
 create mode 100644 arch/arm/dts/s700.dtsi
 create mode 100644 include/dt-bindings/clock/actions,s700-cmu.h

Comments

Manivannan Sadhasivam Jan. 5, 2019, 6:41 p.m. UTC | #1 
On Thu, Jan 03, 2019 at 06:56:20PM +0530, Amit Singh Tomar wrote:
> This patch adds .dtsi file(sync with Linux 4.20) and required binding
> for S700 SoC that is a 64-bit Quad-core ARM Cortex-A53 cores.
> 
> Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
> ---
>  arch/arm/dts/s700.dtsi                       | 193 +++++++++++++++++++++++++++
>  include/dt-bindings/clock/actions,s700-cmu.h | 118 ++++++++++++++++
>  2 files changed, 311 insertions(+)
>  create mode 100644 arch/arm/dts/s700.dtsi
>  create mode 100644 include/dt-bindings/clock/actions,s700-cmu.h
> 
> diff --git a/arch/arm/dts/s700.dtsi b/arch/arm/dts/s700.dtsi
> new file mode 100644
> index 0000000..a74c75a
> --- /dev/null
> +++ b/arch/arm/dts/s700.dtsi
> @@ -0,0 +1,193 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2017 Andreas Färber
> + */
> +
> +#include <dt-bindings/clock/actions,s700-cmu.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> +	compatible = "actions,s700";
> +	interrupt-parent = <&gic>;
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <2>;
> +		#size-cells = <0>;
> +
> +		cpu0: cpu@0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			reg = <0x0 0x0>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu1: cpu@1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			reg = <0x0 0x1>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu2: cpu@2 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			reg = <0x0 0x2>;
> +			enable-method = "psci";
> +		};
> +
> +		cpu3: cpu@3 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53", "arm,armv8";
> +			reg = <0x0 0x3>;
> +			enable-method = "psci";
> +		};
> +	};
> +
> +	reserved-memory {
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		secmon@1f000000 {
> +			reg = <0x0 0x1f000000 0x0 0x1000000>;
> +			no-map;
> +		};
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-0.2";
> +		method = "smc";
> +	};
> +
> +	arm-pmu {
> +		compatible = "arm,cortex-a53-pmu";
> +		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
> +		             <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
> +		             <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
> +		             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13
> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 14
> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 11
> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
> +			     <GIC_PPI 10
> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> +	};
> +
> +	hosc: hosc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <24000000>;
> +		#clock-cells = <0>;
> +	};
> +
> +	losc: losc {
> +		compatible = "fixed-clock";
> +		clock-frequency = <32768>;
> +		#clock-cells = <0>;
> +	};
> +
> +	soc {
> +		u-boot,dm-pre-reloc;
> +		compatible = "simple-bus";
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +
> +		gic: interrupt-controller@e00f1000 {
> +			compatible = "arm,gic-400";
> +			reg = <0x0 0xe00f1000 0x0 0x1000>,
> +			      <0x0 0xe00f2000 0x0 0x2000>,
> +			      <0x0 0xe00f4000 0x0 0x2000>,
> +			      <0x0 0xe00f6000 0x0 0x2000>;
> +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
> +			interrupt-controller;
> +			#interrupt-cells = <3>;
> +		};
> +
> +		uart0: serial@e0120000 {
> +			compatible = "actions,s900-uart", "actions,owl-uart";
> +			reg = <0x0 0xe0120000 0x0 0x2000>;
> +			clocks = <&cmu CLK_UART0>;
> +			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +		};
> +
> +		uart1: serial@e0122000 {
> +			compatible = "actions,s900-uart", "actions,owl-uart";
> +			reg = <0x0 0xe0122000 0x0 0x2000>;
> +			clocks = <&cmu CLK_UART1>;
> +			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@e0124000 {
> +			compatible = "actions,s900-uart", "actions,owl-uart";
> +			reg = <0x0 0xe0124000 0x0 0x2000>;
> +			clocks = <&cmu CLK_UART2>;
> +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +		};
> +
> +		uart3: serial@e0126000 {
> +			u-boot,dm-pre-reloc;

It would be best to keep this DTS unchanged with Linux and add the
u-boot specific bits in -u-boot.dtsi.

> +			compatible = "actions,s900-uart", "actions,owl-uart";
> +			reg = <0x0 0xe0126000 0x0 0x2000>;
> +			clocks = <&cmu CLK_UART3>;
> +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +		};
> +
> +		uart4: serial@e0128000 {
> +			compatible = "actions,s900-uart", "actions,owl-uart";
> +			reg = <0x0 0xe0128000 0x0 0x2000>;
> +			clocks = <&cmu CLK_UART4>;
> +			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +		};
> +
> +		uart5: serial@e012a000 {
> +			compatible = "actions,s900-uart", "actions,owl-uart";
> +			reg = <0x0 0xe012a000 0x0 0x2000>;
> +			clocks = <&cmu CLK_UART5>;
> +			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +		};
> +
> +		uart6: serial@e012c000 {
> +			compatible = "actions,s900-uart", "actions,owl-uart";
> +			reg = <0x0 0xe012c000 0x0 0x2000>;
> +			clocks = <&cmu CLK_UART6>;
> +			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> +			status = "disabled";
> +		};
> +
> +		cmu: clock-controller@e0168000 {
> +			u-boot,dm-pre-reloc;

Same as above comment.

Thanks,
Mani

> +			compatible = "actions,s700-cmu";
> +			reg = <0x0 0xe0168000 0x0 0x1000>;
> +			clocks = <&hosc>, <&losc>;
> +			#clock-cells = <1>;
> +		};
> +
> +		sps: power-controller@e01b0100 {
> +			compatible = "actions,s700-sps";
> +			reg = <0x0 0xe01b0100 0x0 0x100>;
> +			#power-domain-cells = <1>;
> +		};
> +
> +		timer: timer@e024c000 {
> +			compatible = "actions,s700-timer";
> +			reg = <0x0 0xe024c000 0x0 0x4000>;
> +			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "timer1";
> +		};
> +	};
> +};
> diff --git a/include/dt-bindings/clock/actions,s700-cmu.h b/include/dt-bindings/clock/actions,s700-cmu.h
> new file mode 100644
> index 0000000..3e19429
> --- /dev/null
> +++ b/include/dt-bindings/clock/actions,s700-cmu.h
> @@ -0,0 +1,118 @@
> +/* SPDX-License-Identifier: GPL-2.0
> + *
> + * Device Tree binding constants for Actions Semi S700 Clock Management Unit
> + *
> + * Copyright (c) 2014 Actions Semi Inc.
> + * Author: David Liu <liuwei@actions-semi.com>
> + *
> + * Author: Pathiban Nallathambi <pn@denx.de>
> + * Author: Saravanan Sekar <sravanhome@gmail.com>
> + */
> +
> +#ifndef __DT_BINDINGS_CLOCK_S700_H
> +#define __DT_BINDINGS_CLOCK_S700_H
> +
> +#define CLK_NONE			0
> +
> +/* pll clocks */
> +#define CLK_CORE_PLL			1
> +#define CLK_DEV_PLL			2
> +#define CLK_DDR_PLL			3
> +#define CLK_NAND_PLL			4
> +#define CLK_DISPLAY_PLL			5
> +#define CLK_TVOUT_PLL			6
> +#define CLK_CVBS_PLL			7
> +#define CLK_AUDIO_PLL			8
> +#define CLK_ETHERNET_PLL		9
> +
> +/* system clock */
> +#define CLK_CPU				10
> +#define CLK_DEV				11
> +#define CLK_AHB				12
> +#define CLK_APB				13
> +#define CLK_DMAC			14
> +#define CLK_NOC0_CLK_MUX		15
> +#define CLK_NOC1_CLK_MUX		16
> +#define CLK_HP_CLK_MUX			17
> +#define CLK_HP_CLK_DIV			18
> +#define CLK_NOC1_CLK_DIV		19
> +#define CLK_NOC0			20
> +#define CLK_NOC1			21
> +#define CLK_SENOR_SRC			22
> +
> +/* peripheral device clock */
> +#define CLK_GPIO			23
> +#define CLK_TIMER			24
> +#define CLK_DSI				25
> +#define CLK_CSI				26
> +#define CLK_SI				27
> +#define CLK_DE				28
> +#define CLK_HDE				29
> +#define CLK_VDE				30
> +#define CLK_VCE				31
> +#define CLK_NAND			32
> +#define CLK_SD0				33
> +#define CLK_SD1				34
> +#define CLK_SD2				35
> +
> +#define CLK_UART0			36
> +#define CLK_UART1			37
> +#define CLK_UART2			38
> +#define CLK_UART3			39
> +#define CLK_UART4			40
> +#define CLK_UART5			41
> +#define CLK_UART6			42
> +
> +#define CLK_PWM0			43
> +#define CLK_PWM1			44
> +#define CLK_PWM2			45
> +#define CLK_PWM3			46
> +#define CLK_PWM4			47
> +#define CLK_PWM5			48
> +#define CLK_GPU3D			49
> +
> +#define CLK_I2C0			50
> +#define CLK_I2C1			51
> +#define CLK_I2C2			52
> +#define CLK_I2C3			53
> +
> +#define CLK_SPI0			54
> +#define CLK_SPI1			55
> +#define CLK_SPI2			56
> +#define CLK_SPI3			57
> +
> +#define CLK_USB3_480MPLL0		58
> +#define CLK_USB3_480MPHY0		59
> +#define CLK_USB3_5GPHY			60
> +#define CLK_USB3_CCE			61
> +#define CLK_USB3_MAC			62
> +
> +#define CLK_LCD				63
> +#define CLK_HDMI_AUDIO			64
> +#define CLK_I2SRX			65
> +#define CLK_I2STX			66
> +
> +#define CLK_SENSOR0			67
> +#define CLK_SENSOR1			68
> +
> +#define CLK_HDMI_DEV			69
> +
> +#define CLK_ETHERNET			70
> +#define CLK_RMII_REF			71
> +
> +#define CLK_USB2H0_PLLEN		72
> +#define CLK_USB2H0_PHY			73
> +#define CLK_USB2H0_CCE			74
> +#define CLK_USB2H1_PLLEN		75
> +#define CLK_USB2H1_PHY			76
> +#define CLK_USB2H1_CCE			77
> +
> +#define CLK_TVOUT			78
> +
> +#define CLK_THERMAL_SENSOR		79
> +
> +#define CLK_IRC_SWITCH			80
> +#define CLK_PCM1			81
> +#define CLK_NR_CLKS			(CLK_PCM1 + 1)
> +
> +#endif /* __DT_BINDINGS_CLOCK_S700_H */
> -- 
> 2.7.4
>
Andre Przywara Jan. 6, 2019, 1:43 a.m. UTC | #2 
On 05/01/2019 18:41, Manivannan Sadhasivam wrote:
> On Thu, Jan 03, 2019 at 06:56:20PM +0530, Amit Singh Tomar wrote:
>> This patch adds .dtsi file(sync with Linux 4.20) and required binding
>> for S700 SoC that is a 64-bit Quad-core ARM Cortex-A53 cores.
>>
>> Signed-off-by: Amit Singh Tomar <amittomer25@gmail.com>
>> ---
>>  arch/arm/dts/s700.dtsi                       | 193 +++++++++++++++++++++++++++
>>  include/dt-bindings/clock/actions,s700-cmu.h | 118 ++++++++++++++++
>>  2 files changed, 311 insertions(+)
>>  create mode 100644 arch/arm/dts/s700.dtsi
>>  create mode 100644 include/dt-bindings/clock/actions,s700-cmu.h
>>
>> diff --git a/arch/arm/dts/s700.dtsi b/arch/arm/dts/s700.dtsi
>> new file mode 100644
>> index 0000000..a74c75a
>> --- /dev/null
>> +++ b/arch/arm/dts/s700.dtsi
>> @@ -0,0 +1,193 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (c) 2017 Andreas Färber
>> + */
>> +
>> +#include <dt-bindings/clock/actions,s700-cmu.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> +/ {
>> +	compatible = "actions,s700";
>> +	interrupt-parent = <&gic>;
>> +	#address-cells = <2>;
>> +	#size-cells = <2>;
>> +
>> +	cpus {
>> +		#address-cells = <2>;
>> +		#size-cells = <0>;
>> +
>> +		cpu0: cpu@0 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a53", "arm,armv8";
>> +			reg = <0x0 0x0>;
>> +			enable-method = "psci";
>> +		};
>> +
>> +		cpu1: cpu@1 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a53", "arm,armv8";
>> +			reg = <0x0 0x1>;
>> +			enable-method = "psci";
>> +		};
>> +
>> +		cpu2: cpu@2 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a53", "arm,armv8";
>> +			reg = <0x0 0x2>;
>> +			enable-method = "psci";
>> +		};
>> +
>> +		cpu3: cpu@3 {
>> +			device_type = "cpu";
>> +			compatible = "arm,cortex-a53", "arm,armv8";
>> +			reg = <0x0 0x3>;
>> +			enable-method = "psci";
>> +		};
>> +	};
>> +
>> +	reserved-memory {
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +
>> +		secmon@1f000000 {
>> +			reg = <0x0 0x1f000000 0x0 0x1000000>;
>> +			no-map;
>> +		};
>> +	};
>> +
>> +	psci {
>> +		compatible = "arm,psci-0.2";
>> +		method = "smc";
>> +	};
>> +
>> +	arm-pmu {
>> +		compatible = "arm,cortex-a53-pmu";
>> +		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
>> +		             <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
>> +		             <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
>> +		             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
>> +		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
>> +	};
>> +
>> +	timer {
>> +		compatible = "arm,armv8-timer";
>> +		interrupts = <GIC_PPI 13
>> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 14
>> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 11
>> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 10
>> +			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> +	};
>> +
>> +	hosc: hosc {
>> +		compatible = "fixed-clock";
>> +		clock-frequency = <24000000>;
>> +		#clock-cells = <0>;
>> +	};
>> +
>> +	losc: losc {
>> +		compatible = "fixed-clock";
>> +		clock-frequency = <32768>;
>> +		#clock-cells = <0>;
>> +	};
>> +
>> +	soc {
>> +		u-boot,dm-pre-reloc;
>> +		compatible = "simple-bus";
>> +		#address-cells = <2>;
>> +		#size-cells = <2>;
>> +		ranges;
>> +
>> +		gic: interrupt-controller@e00f1000 {
>> +			compatible = "arm,gic-400";
>> +			reg = <0x0 0xe00f1000 0x0 0x1000>,
>> +			      <0x0 0xe00f2000 0x0 0x2000>,
>> +			      <0x0 0xe00f4000 0x0 0x2000>,
>> +			      <0x0 0xe00f6000 0x0 0x2000>;
>> +			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> +			interrupt-controller;
>> +			#interrupt-cells = <3>;
>> +		};
>> +
>> +		uart0: serial@e0120000 {
>> +			compatible = "actions,s900-uart", "actions,owl-uart";
>> +			reg = <0x0 0xe0120000 0x0 0x2000>;
>> +			clocks = <&cmu CLK_UART0>;
>> +			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
>> +			status = "disabled";
>> +		};
>> +
>> +		uart1: serial@e0122000 {
>> +			compatible = "actions,s900-uart", "actions,owl-uart";
>> +			reg = <0x0 0xe0122000 0x0 0x2000>;
>> +			clocks = <&cmu CLK_UART1>;
>> +			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
>> +			status = "disabled";
>> +		};
>> +
>> +		uart2: serial@e0124000 {
>> +			compatible = "actions,s900-uart", "actions,owl-uart";
>> +			reg = <0x0 0xe0124000 0x0 0x2000>;
>> +			clocks = <&cmu CLK_UART2>;
>> +			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
>> +			status = "disabled";
>> +		};
>> +
>> +		uart3: serial@e0126000 {
>> +			u-boot,dm-pre-reloc;
> 
> It would be best to keep this DTS unchanged with Linux and add the
> u-boot specific bits in -u-boot.dtsi.

Ah, good catch, I agree on the -u-boot.dtsi approach.

Amit, please don't claim it's "sync with Linux" if it isn't. At least
document this change.

Also there is another instance above, directly on the /soc node.

Maybe we should do as others do and set DM_FLAG_PRE_RELOC on the driver,
to avoid changing the DT at all?

Cheers,
Andre

>> +			compatible = "actions,s900-uart", "actions,owl-uart";
>> +			reg = <0x0 0xe0126000 0x0 0x2000>;
>> +			clocks = <&cmu CLK_UART3>;
>> +			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>> +			status = "disabled";
>> +		};
>> +
>> +		uart4: serial@e0128000 {
>> +			compatible = "actions,s900-uart", "actions,owl-uart";
>> +			reg = <0x0 0xe0128000 0x0 0x2000>;
>> +			clocks = <&cmu CLK_UART4>;
>> +			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
>> +			status = "disabled";
>> +		};
>> +
>> +		uart5: serial@e012a000 {
>> +			compatible = "actions,s900-uart", "actions,owl-uart";
>> +			reg = <0x0 0xe012a000 0x0 0x2000>;
>> +			clocks = <&cmu CLK_UART5>;
>> +			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
>> +			status = "disabled";
>> +		};
>> +
>> +		uart6: serial@e012c000 {
>> +			compatible = "actions,s900-uart", "actions,owl-uart";
>> +			reg = <0x0 0xe012c000 0x0 0x2000>;
>> +			clocks = <&cmu CLK_UART6>;
>> +			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
>> +			status = "disabled";
>> +		};
>> +
>> +		cmu: clock-controller@e0168000 {
>> +			u-boot,dm-pre-reloc;
> 
> Same as above comment.
> 
> Thanks,
> Mani
> 
>> +			compatible = "actions,s700-cmu";
>> +			reg = <0x0 0xe0168000 0x0 0x1000>;
>> +			clocks = <&hosc>, <&losc>;
>> +			#clock-cells = <1>;
>> +		};
>> +
>> +		sps: power-controller@e01b0100 {
>> +			compatible = "actions,s700-sps";
>> +			reg = <0x0 0xe01b0100 0x0 0x100>;
>> +			#power-domain-cells = <1>;
>> +		};
>> +
>> +		timer: timer@e024c000 {
>> +			compatible = "actions,s700-timer";
>> +			reg = <0x0 0xe024c000 0x0 0x4000>;
>> +			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
>> +			interrupt-names = "timer1";
>> +		};
>> +	};
>> +};
>> diff --git a/include/dt-bindings/clock/actions,s700-cmu.h b/include/dt-bindings/clock/actions,s700-cmu.h
>> new file mode 100644
>> index 0000000..3e19429
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/actions,s700-cmu.h
>> @@ -0,0 +1,118 @@
>> +/* SPDX-License-Identifier: GPL-2.0
>> + *
>> + * Device Tree binding constants for Actions Semi S700 Clock Management Unit
>> + *
>> + * Copyright (c) 2014 Actions Semi Inc.
>> + * Author: David Liu <liuwei@actions-semi.com>
>> + *
>> + * Author: Pathiban Nallathambi <pn@denx.de>
>> + * Author: Saravanan Sekar <sravanhome@gmail.com>
>> + */
>> +
>> +#ifndef __DT_BINDINGS_CLOCK_S700_H
>> +#define __DT_BINDINGS_CLOCK_S700_H
>> +
>> +#define CLK_NONE			0
>> +
>> +/* pll clocks */
>> +#define CLK_CORE_PLL			1
>> +#define CLK_DEV_PLL			2
>> +#define CLK_DDR_PLL			3
>> +#define CLK_NAND_PLL			4
>> +#define CLK_DISPLAY_PLL			5
>> +#define CLK_TVOUT_PLL			6
>> +#define CLK_CVBS_PLL			7
>> +#define CLK_AUDIO_PLL			8
>> +#define CLK_ETHERNET_PLL		9
>> +
>> +/* system clock */
>> +#define CLK_CPU				10
>> +#define CLK_DEV				11
>> +#define CLK_AHB				12
>> +#define CLK_APB				13
>> +#define CLK_DMAC			14
>> +#define CLK_NOC0_CLK_MUX		15
>> +#define CLK_NOC1_CLK_MUX		16
>> +#define CLK_HP_CLK_MUX			17
>> +#define CLK_HP_CLK_DIV			18
>> +#define CLK_NOC1_CLK_DIV		19
>> +#define CLK_NOC0			20
>> +#define CLK_NOC1			21
>> +#define CLK_SENOR_SRC			22
>> +
>> +/* peripheral device clock */
>> +#define CLK_GPIO			23
>> +#define CLK_TIMER			24
>> +#define CLK_DSI				25
>> +#define CLK_CSI				26
>> +#define CLK_SI				27
>> +#define CLK_DE				28
>> +#define CLK_HDE				29
>> +#define CLK_VDE				30
>> +#define CLK_VCE				31
>> +#define CLK_NAND			32
>> +#define CLK_SD0				33
>> +#define CLK_SD1				34
>> +#define CLK_SD2				35
>> +
>> +#define CLK_UART0			36
>> +#define CLK_UART1			37
>> +#define CLK_UART2			38
>> +#define CLK_UART3			39
>> +#define CLK_UART4			40
>> +#define CLK_UART5			41
>> +#define CLK_UART6			42
>> +
>> +#define CLK_PWM0			43
>> +#define CLK_PWM1			44
>> +#define CLK_PWM2			45
>> +#define CLK_PWM3			46
>> +#define CLK_PWM4			47
>> +#define CLK_PWM5			48
>> +#define CLK_GPU3D			49
>> +
>> +#define CLK_I2C0			50
>> +#define CLK_I2C1			51
>> +#define CLK_I2C2			52
>> +#define CLK_I2C3			53
>> +
>> +#define CLK_SPI0			54
>> +#define CLK_SPI1			55
>> +#define CLK_SPI2			56
>> +#define CLK_SPI3			57
>> +
>> +#define CLK_USB3_480MPLL0		58
>> +#define CLK_USB3_480MPHY0		59
>> +#define CLK_USB3_5GPHY			60
>> +#define CLK_USB3_CCE			61
>> +#define CLK_USB3_MAC			62
>> +
>> +#define CLK_LCD				63
>> +#define CLK_HDMI_AUDIO			64
>> +#define CLK_I2SRX			65
>> +#define CLK_I2STX			66
>> +
>> +#define CLK_SENSOR0			67
>> +#define CLK_SENSOR1			68
>> +
>> +#define CLK_HDMI_DEV			69
>> +
>> +#define CLK_ETHERNET			70
>> +#define CLK_RMII_REF			71
>> +
>> +#define CLK_USB2H0_PLLEN		72
>> +#define CLK_USB2H0_PHY			73
>> +#define CLK_USB2H0_CCE			74
>> +#define CLK_USB2H1_PLLEN		75
>> +#define CLK_USB2H1_PHY			76
>> +#define CLK_USB2H1_CCE			77
>> +
>> +#define CLK_TVOUT			78
>> +
>> +#define CLK_THERMAL_SENSOR		79
>> +
>> +#define CLK_IRC_SWITCH			80
>> +#define CLK_PCM1			81
>> +#define CLK_NR_CLKS			(CLK_PCM1 + 1)
>> +
>> +#endif /* __DT_BINDINGS_CLOCK_S700_H */
>> -- 
>> 2.7.4
>>
Amit Tomer Jan. 6, 2019, 2:16 a.m. UTC | #3 
> Ah, good catch, I agree on the -u-boot.dtsi approach.

Thanks for talking about it( I was expecting this comment)

> Amit, please don't claim it's "sync with Linux" if it isn't. At least
> document this change.

Yeah, I was aware of this situation but rightly so, I should have documented
it in commit messages.
Sorry, I didn't.

> Also there is another instance above, directly on the /soc node.
>
> Maybe we should do as others do and set DM_FLAG_PRE_RELOC on the driver,
> to avoid changing the DT at all?

Yeah, I had something similar in my mind(same was suggested in this
thread[1] few days back)
but wasn't able to test it.

Also, if you see current s900.dtsi in u-boot , it uses those flag in
dtsi itself.

Thanks
-Amit.

[1] : https://lists.denx.de/pipermail/u-boot/2019-January/353438.html

Hate to get up in morning, its cold out here(with bit of rain too) :(
diff mbox series

Patch

diff --git a/arch/arm/dts/s700.dtsi b/arch/arm/dts/s700.dtsi
new file mode 100644
index 0000000..a74c75a
--- /dev/null
+++ b/arch/arm/dts/s700.dtsi
@@ -0,0 +1,193 @@ 
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 Andreas Färber
+ */
+
+#include <dt-bindings/clock/actions,s700-cmu.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "actions,s700";
+	interrupt-parent = <&gic>;
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x0>;
+			enable-method = "psci";
+		};
+
+		cpu1: cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x1>;
+			enable-method = "psci";
+		};
+
+		cpu2: cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x2>;
+			enable-method = "psci";
+		};
+
+		cpu3: cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53", "arm,armv8";
+			reg = <0x0 0x3>;
+			enable-method = "psci";
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		secmon@1f000000 {
+			reg = <0x0 0x1f000000 0x0 0x1000000>;
+			no-map;
+		};
+	};
+
+	psci {
+		compatible = "arm,psci-0.2";
+		method = "smc";
+	};
+
+	arm-pmu {
+		compatible = "arm,cortex-a53-pmu";
+		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+		             <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10
+			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	hosc: hosc {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		#clock-cells = <0>;
+	};
+
+	losc: losc {
+		compatible = "fixed-clock";
+		clock-frequency = <32768>;
+		#clock-cells = <0>;
+	};
+
+	soc {
+		u-boot,dm-pre-reloc;
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		gic: interrupt-controller@e00f1000 {
+			compatible = "arm,gic-400";
+			reg = <0x0 0xe00f1000 0x0 0x1000>,
+			      <0x0 0xe00f2000 0x0 0x2000>,
+			      <0x0 0xe00f4000 0x0 0x2000>,
+			      <0x0 0xe00f6000 0x0 0x2000>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+		};
+
+		uart0: serial@e0120000 {
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe0120000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART0>;
+			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart1: serial@e0122000 {
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe0122000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART1>;
+			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart2: serial@e0124000 {
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe0124000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART2>;
+			interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart3: serial@e0126000 {
+			u-boot,dm-pre-reloc;
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe0126000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART3>;
+			interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart4: serial@e0128000 {
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe0128000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART4>;
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart5: serial@e012a000 {
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe012a000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART5>;
+			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		uart6: serial@e012c000 {
+			compatible = "actions,s900-uart", "actions,owl-uart";
+			reg = <0x0 0xe012c000 0x0 0x2000>;
+			clocks = <&cmu CLK_UART6>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+		};
+
+		cmu: clock-controller@e0168000 {
+			u-boot,dm-pre-reloc;
+			compatible = "actions,s700-cmu";
+			reg = <0x0 0xe0168000 0x0 0x1000>;
+			clocks = <&hosc>, <&losc>;
+			#clock-cells = <1>;
+		};
+
+		sps: power-controller@e01b0100 {
+			compatible = "actions,s700-sps";
+			reg = <0x0 0xe01b0100 0x0 0x100>;
+			#power-domain-cells = <1>;
+		};
+
+		timer: timer@e024c000 {
+			compatible = "actions,s700-timer";
+			reg = <0x0 0xe024c000 0x0 0x4000>;
+			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "timer1";
+		};
+	};
+};
diff --git a/include/dt-bindings/clock/actions,s700-cmu.h b/include/dt-bindings/clock/actions,s700-cmu.h
new file mode 100644
index 0000000..3e19429
--- /dev/null
+++ b/include/dt-bindings/clock/actions,s700-cmu.h
@@ -0,0 +1,118 @@ 
+/* SPDX-License-Identifier: GPL-2.0
+ *
+ * Device Tree binding constants for Actions Semi S700 Clock Management Unit
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Author: David Liu <liuwei@actions-semi.com>
+ *
+ * Author: Pathiban Nallathambi <pn@denx.de>
+ * Author: Saravanan Sekar <sravanhome@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_S700_H
+#define __DT_BINDINGS_CLOCK_S700_H
+
+#define CLK_NONE			0
+
+/* pll clocks */
+#define CLK_CORE_PLL			1
+#define CLK_DEV_PLL			2
+#define CLK_DDR_PLL			3
+#define CLK_NAND_PLL			4
+#define CLK_DISPLAY_PLL			5
+#define CLK_TVOUT_PLL			6
+#define CLK_CVBS_PLL			7
+#define CLK_AUDIO_PLL			8
+#define CLK_ETHERNET_PLL		9
+
+/* system clock */
+#define CLK_CPU				10
+#define CLK_DEV				11
+#define CLK_AHB				12
+#define CLK_APB				13
+#define CLK_DMAC			14
+#define CLK_NOC0_CLK_MUX		15
+#define CLK_NOC1_CLK_MUX		16
+#define CLK_HP_CLK_MUX			17
+#define CLK_HP_CLK_DIV			18
+#define CLK_NOC1_CLK_DIV		19
+#define CLK_NOC0			20
+#define CLK_NOC1			21
+#define CLK_SENOR_SRC			22
+
+/* peripheral device clock */
+#define CLK_GPIO			23
+#define CLK_TIMER			24
+#define CLK_DSI				25
+#define CLK_CSI				26
+#define CLK_SI				27
+#define CLK_DE				28
+#define CLK_HDE				29
+#define CLK_VDE				30
+#define CLK_VCE				31
+#define CLK_NAND			32
+#define CLK_SD0				33
+#define CLK_SD1				34
+#define CLK_SD2				35
+
+#define CLK_UART0			36
+#define CLK_UART1			37
+#define CLK_UART2			38
+#define CLK_UART3			39
+#define CLK_UART4			40
+#define CLK_UART5			41
+#define CLK_UART6			42
+
+#define CLK_PWM0			43
+#define CLK_PWM1			44
+#define CLK_PWM2			45
+#define CLK_PWM3			46
+#define CLK_PWM4			47
+#define CLK_PWM5			48
+#define CLK_GPU3D			49
+
+#define CLK_I2C0			50
+#define CLK_I2C1			51
+#define CLK_I2C2			52
+#define CLK_I2C3			53
+
+#define CLK_SPI0			54
+#define CLK_SPI1			55
+#define CLK_SPI2			56
+#define CLK_SPI3			57
+
+#define CLK_USB3_480MPLL0		58
+#define CLK_USB3_480MPHY0		59
+#define CLK_USB3_5GPHY			60
+#define CLK_USB3_CCE			61
+#define CLK_USB3_MAC			62
+
+#define CLK_LCD				63
+#define CLK_HDMI_AUDIO			64
+#define CLK_I2SRX			65
+#define CLK_I2STX			66
+
+#define CLK_SENSOR0			67
+#define CLK_SENSOR1			68
+
+#define CLK_HDMI_DEV			69
+
+#define CLK_ETHERNET			70
+#define CLK_RMII_REF			71
+
+#define CLK_USB2H0_PLLEN		72
+#define CLK_USB2H0_PHY			73
+#define CLK_USB2H0_CCE			74
+#define CLK_USB2H1_PLLEN		75
+#define CLK_USB2H1_PHY			76
+#define CLK_USB2H1_CCE			77
+
+#define CLK_TVOUT			78
+
+#define CLK_THERMAL_SENSOR		79
+
+#define CLK_IRC_SWITCH			80
+#define CLK_PCM1			81
+#define CLK_NR_CLKS			(CLK_PCM1 + 1)
+
+#endif /* __DT_BINDINGS_CLOCK_S700_H */