From patchwork Fri Nov 30 02:54:57 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aditya Prayoga X-Patchwork-Id: 1005766 X-Patchwork-Delegate: sr@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=kobol.io Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 435fG81X1Sz9s3C for ; Fri, 30 Nov 2018 13:58:08 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id DDF45C22318; Fri, 30 Nov 2018 02:56:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E41C5C2206C; Fri, 30 Nov 2018 02:55:58 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 16ED8C222EC; Fri, 30 Nov 2018 02:55:28 +0000 (UTC) Received: from relay12.mail.gandi.net (relay12.mail.gandi.net [217.70.178.232]) by lists.denx.de (Postfix) with ESMTPS id 3A621C22318 for ; Fri, 30 Nov 2018 02:55:24 +0000 (UTC) Received: from ubuntuVM.lan (unknown [36.79.171.6]) (Authenticated sender: aditya@kobol.io) by relay12.mail.gandi.net (Postfix) with ESMTPSA id 0B43B200002; Fri, 30 Nov 2018 02:55:20 +0000 (UTC) From: Aditya Prayoga To: u-boot@lists.denx.de Date: Fri, 30 Nov 2018 10:54:57 +0800 Message-Id: <1543546499-106725-5-git-send-email-aditya@kobol.io> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1543546499-106725-1-git-send-email-aditya@kobol.io> References: <1543546499-106725-1-git-send-email-aditya@kobol.io> Cc: Baruch Siach , Gauthier Provost , Aditya Prayoga , Dennis Gilmore , Stefan Roese Subject: [U-Boot] [PATCH v2 4/6] arm: mvebu: helios4: Reduce U-Boot image size X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Remove unused I2C support in SPL and use simple_malloc functions to reduce SPL image size. Since Helios4 does not have any PCIe allocated on SerDes, remove PCI support. MTD layer on top of SPI flash is not needed, remove it also. Signed-off-by: Aditya Prayoga --- configs/helios4_defconfig | 5 +---- include/configs/helios4.h | 6 ------ 2 files changed, 1 insertion(+), 10 deletions(-) diff --git a/configs/helios4_defconfig b/configs/helios4_defconfig index 69dd774..53995fe 100644 --- a/configs/helios4_defconfig +++ b/configs/helios4_defconfig @@ -8,6 +8,7 @@ CONFIG_TARGET_HELIOS4=y CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y CONFIG_SPL_MMC_SUPPORT=y CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL=y CONFIG_DEBUG_UART_BASE=0xd0012000 CONFIG_DEBUG_UART_CLOCK=250000000 @@ -20,12 +21,10 @@ CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_BOARDINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x141 -CONFIG_SPL_I2C_SUPPORT=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y -CONFIG_CMD_PCI=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y @@ -52,11 +51,9 @@ CONFIG_MMC_SDHCI_MV=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_BAR=y CONFIG_SPI_FLASH_WINBOND=y -CONFIG_SPI_FLASH_MTD=y CONFIG_PHY_GIGE=y CONFIG_MVNETA=y CONFIG_MII=y -CONFIG_PCI=y CONFIG_SCSI=y CONFIG_DEBUG_UART_SHIFT=2 CONFIG_SYS_NS16550=y diff --git a/include/configs/helios4.h b/include/configs/helios4.h index c71055f..e665340 100644 --- a/include/configs/helios4.h +++ b/include/configs/helios4.h @@ -54,12 +54,6 @@ #define CONFIG_PHY_MARVELL /* there is a marvell phy */ #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ -/* PCIe support */ -#ifndef CONFIG_SPL_BUILD -#define CONFIG_PCI_MVEBU -#define CONFIG_PCI_SCAN_SHOW -#endif - /* Keep device tree and initrd in lower memory so the kernel can access them */ #define RELOCATION_LIMITS_ENV_SETTINGS \ "fdt_high=0x10000000\0" \