From patchwork Fri Nov 16 13:57:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philippe REYNES X-Patchwork-Id: 998965 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=softathome.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 42xKZY587Gz9s0t for ; Sat, 17 Nov 2018 00:58:29 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 50080C222FF; Fri, 16 Nov 2018 13:58:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 529DEC2250B; Fri, 16 Nov 2018 13:57:16 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C1CD6C224E8; Fri, 16 Nov 2018 13:57:12 +0000 (UTC) Received: from vrout30.yaziba.net (vrout30.yaziba.net [185.56.204.33]) by lists.denx.de (Postfix) with ESMTPS id D05A1C224E8 for ; Fri, 16 Nov 2018 13:57:11 +0000 (UTC) Received: from mtaout20.int.yaziba.net (mtaout20.int.yaziba.net [10.4.20.37]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by vrout30.yaziba.net (mx10.yaziba.net) with ESMTPS id 65DB351E8D; Fri, 16 Nov 2018 14:57:10 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by mtaout20.int.yaziba.net (Postfix) with ESMTP id 6FCDE160451; Fri, 16 Nov 2018 14:57:10 +0100 (CET) X-Virus-Scanned: amavisd-new at mtaout20.int.yaziba.net Received: from mtaout20.int.yaziba.net ([127.0.0.1]) by localhost (mtaout20.int.yaziba.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 1BdWSoKbNXmK; Fri, 16 Nov 2018 14:57:10 +0100 (CET) Received: from sahnlpt0333.softathome.com (unknown [149.6.166.170]) by mtaout20.int.yaziba.net (Postfix) with ESMTPSA id 54F7D160422; Fri, 16 Nov 2018 14:57:10 +0100 (CET) From: Philippe Reynes To: miquel.raynal@bootlin.com, boris.brezillon@bootlin.com Date: Fri, 16 Nov 2018 14:57:01 +0100 Message-Id: <1542376624-17495-5-git-send-email-philippe.reynes@softathome.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1542376624-17495-1-git-send-email-philippe.reynes@softathome.com> References: <1542376624-17495-1-git-send-email-philippe.reynes@softathome.com> X-DRWEB-SCAN: ok X-CLAMAV-SCAN: ok X-VRSPAM-SCORE: 0 X-VRSPAM-STATE: legit X-VRSPAM-CAUSE: gggruggvucftvghtrhhoucdtuddrgedtkedrleejgdehjecutefuodetggdotefrucfrrhhofhhilhgvmecuggftfghnshhusghstghrihgsvgenuceurghilhhouhhtmecufedttdenucenucfjughrpefhvffufffkofgjfhestddtredtredttdenucfhrhhomheprfhhihhlihhpphgvucftvgihnhgvshcuoehphhhilhhiphhpvgdrrhgvhihnvghssehsohhfthgrthhhohhmvgdrtghomheqnecukfhppedugeelrdeirdduieeirddujedtnecurfgrrhgrmhepmhhouggvpehsmhhtphhouhht X-VRSPAM-EXTCAUSE: mhhouggvpehsmhhtphhouhht Cc: u-boot@lists.denx.de Subject: [U-Boot] [RFC][PATCH V0 4/7] arm: asm: io.h: define readX_relaxed and writeX_relaxed X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Philippe Reynes --- arch/arm/include/asm/io.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h index 5df7472..ab6bc59 100644 --- a/arch/arm/include/asm/io.h +++ b/arch/arm/include/asm/io.h @@ -123,6 +123,21 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen) #define readq(c) ({ u64 __v = __arch_getq(c); __iormb(); __v; }) /* + * Relaxed I/O memory access primitives. These follow the Device memory + * ordering rules but do not guarantee any ordering relative to Normal memory + * accesses. + */ +#define readb_relaxed(c) ({ u8 __r = __raw_readb(c); __r; }) +#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16)__raw_readw(c)); __r; }) +#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32)__raw_readl(c)); __r; }) +#define readq_relaxed(c) ({ u64 __r = le64_to_cpu((__force __le64)__raw_readq(c)); __r; }) + +#define writeb_relaxed(v,c) ((void)__raw_writeb((v),(c))) +#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)cpu_to_le16(v),(c))) +#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)cpu_to_le32(v),(c))) +#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)cpu_to_le64(v),(c))) + +/* * The compiler seems to be incapable of optimising constants * properly. Spell it out to the compiler in some cases. * These are only valid for small values of "off" (< 1<<12)