From patchwork Tue Sep 4 14:34:01 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Georgii Staroselskii X-Patchwork-Id: 965948 X-Patchwork-Delegate: bmeng.cn@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=emlid.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 424Trt31b6z9sCh for ; Wed, 5 Sep 2018 00:35:25 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 8AE02C2201B; Tue, 4 Sep 2018 14:34:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 48BC4C21FF9; Tue, 4 Sep 2018 14:34:14 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 55B69C21F42; Tue, 4 Sep 2018 14:34:12 +0000 (UTC) Received: from forward105o.mail.yandex.net (forward105o.mail.yandex.net [37.140.190.183]) by lists.denx.de (Postfix) with ESMTPS id A238EC21FB2 for ; Tue, 4 Sep 2018 14:34:11 +0000 (UTC) Received: from mxback10j.mail.yandex.net (mxback10j.mail.yandex.net [IPv6:2a02:6b8:0:1619::113]) by forward105o.mail.yandex.net (Yandex) with ESMTP id EB57A4446831; Tue, 4 Sep 2018 17:34:10 +0300 (MSK) Received: from smtp4j.mail.yandex.net (smtp4j.mail.yandex.net [2a02:6b8:0:1619::15:6]) by mxback10j.mail.yandex.net (nwsmtp/Yandex) with ESMTP id 6OFVTMrdVG-YADecUYO; Tue, 04 Sep 2018 17:34:10 +0300 Received: by smtp4j.mail.yandex.net (nwsmtp/Yandex) with ESMTPSA id BpM7Pg69AJ-Y9KqEkSL; Tue, 04 Sep 2018 17:34:09 +0300 (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (Client certificate not present) From: Georgii Staroselskii To: sjg@chromium.org, bmeng.cn@gmail.com Date: Tue, 4 Sep 2018 17:34:01 +0300 Message-Id: <1536071645-25229-2-git-send-email-georgii.staroselskii@emlid.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1536071645-25229-1-git-send-email-georgii.staroselskii@emlid.com> References: <1536071645-25229-1-git-send-email-georgii.staroselskii@emlid.com> Cc: u-boot@lists.denx.de, andriy.shevchenko@linux.intel.com, fntoth@gmail.com Subject: [U-Boot] [PATCH v2 1/5] x86: cpu: introduce scu_ipc_raw_command() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This interface will be used to configure properly some pins on Merrifield that are shared with SCU. scu_ipc_raw_command() writes SPTR and DPTR registers before sending a command to SCU. This code has been ported from Linux work done by Andy Shevchenko. Signed-off-by: Georgii Staroselskii Reviewed-by: Andy Shevchenko --- arch/x86/include/asm/scu.h | 4 ++++ arch/x86/lib/scu.c | 51 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/arch/x86/include/asm/scu.h b/arch/x86/include/asm/scu.h index 7ce5824..f5ec5a1 100644 --- a/arch/x86/include/asm/scu.h +++ b/arch/x86/include/asm/scu.h @@ -6,6 +6,8 @@ #define _X86_ASM_SCU_IPC_H_ /* IPC defines the following message types */ +#define IPCMSG_INDIRECT_READ 0x02 +#define IPCMSG_INDIRECT_WRITE 0x05 #define IPCMSG_WARM_RESET 0xf0 #define IPCMSG_COLD_RESET 0xf1 #define IPCMSG_SOFT_RESET 0xf2 @@ -23,5 +25,7 @@ struct ipc_ifwi_version { /* Issue commands to the SCU with or without data */ int scu_ipc_simple_command(u32 cmd, u32 sub); int scu_ipc_command(u32 cmd, u32 sub, u32 *in, int inlen, u32 *out, int outlen); +int scu_ipc_raw_command(u32 cmd, u32 sub, u32 *in, int inlen, u32 *out, + int outlen, u32 dptr, u32 sptr); #endif /* _X86_ASM_SCU_IPC_H_ */ diff --git a/arch/x86/lib/scu.c b/arch/x86/lib/scu.c index caa04c6..4054838 100644 --- a/arch/x86/lib/scu.c +++ b/arch/x86/lib/scu.c @@ -102,6 +102,57 @@ static int scu_ipc_cmd(struct ipc_regs *regs, u32 cmd, u32 sub, } /** + * scu_ipc_raw_command() - IPC command with data and pointers + * @cmd: IPC command code. + * @sub: IPC command sub type. + * @in: input data of this IPC command. + * @inlen: input data length in dwords. + * @out: output data of this IPC command. + * @outlen: output data length in dwords. + * @dptr: data writing to SPTR register. + * @sptr: data writing to DPTR register. + * + * Send an IPC command to SCU with input/output data and source/dest pointers. + * + * Return: an IPC error code or 0 on success. + */ +int scu_ipc_raw_command(u32 cmd, u32 sub, u32 *in, int inlen, u32 *out, + int outlen, u32 dptr, u32 sptr) +{ + int inbuflen = DIV_ROUND_UP(inlen, 4); + struct udevice *dev; + struct scu *scu; + int ret; + + ret = syscon_get_by_driver_data(X86_SYSCON_SCU, &dev); + if (ret) + return ret; + + scu = dev_get_priv(dev); + + /* Up to 16 bytes */ + if (inbuflen > 4) + return -EINVAL; + + writel(dptr, &scu->regs->dptr); + writel(sptr, &scu->regs->sptr); + + /* + * SRAM controller doesn't support 8-bit writes, it only + * supports 32-bit writes, so we have to copy input data into + * the temporary buffer, and SCU FW will use the inlen to + * determine the actual input data length in the temporary + * buffer. + */ + + u32 inbuf[4] = {0}; + + memcpy(inbuf, in, inlen); + + return scu_ipc_cmd(scu->regs, cmd, sub, inbuf, inlen, out, outlen); +} + +/** * scu_ipc_simple_command() - send a simple command * @cmd: command * @sub: sub type