From patchwork Wed Jul 25 19:25:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joe Hershberger X-Patchwork-Id: 949356 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=ni.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 41bQJP5KmGz9s0w for ; Thu, 26 Jul 2018 05:28:53 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 6D03EC21DD3; Wed, 25 Jul 2018 19:28:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id EB2CDC21C27; Wed, 25 Jul 2018 19:27:50 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 58602C21C3F; Wed, 25 Jul 2018 19:27:49 +0000 (UTC) Received: from mx0b-00010702.pphosted.com (mx0a-00010702.pphosted.com [148.163.156.75]) by lists.denx.de (Postfix) with ESMTPS id 7AC78C21BE5 for ; Wed, 25 Jul 2018 19:27:48 +0000 (UTC) Received: from pps.filterd (m0098780.ppops.net [127.0.0.1]) by mx0a-00010702.pphosted.com (8.16.0.22/8.16.0.22) with SMTP id w6PJQCcV026184; Wed, 25 Jul 2018 14:27:36 -0500 Received: from ni.com (skprod2.natinst.com [130.164.80.23]) by mx0a-00010702.pphosted.com with ESMTP id 2kewd3ga44-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 25 Jul 2018 14:27:36 -0500 Received: from us-aus-exhub1.ni.corp.natinst.com (us-aus-exhub1.ni.corp.natinst.com [130.164.68.41]) by us-aus-skprod2.natinst.com (8.16.0.22/8.16.0.22) with ESMTPS id w6PJRZFU028908 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 25 Jul 2018 14:27:35 -0500 Received: from us-aus-exch5.ni.corp.natinst.com (130.164.68.15) by us-aus-exhub1.ni.corp.natinst.com (130.164.68.41) with Microsoft SMTP Server (TLS) id 15.0.1156.6; Wed, 25 Jul 2018 14:27:35 -0500 Received: from us-aus-exhub1.ni.corp.natinst.com (130.164.68.41) by us-aus-exch5.ni.corp.natinst.com (130.164.68.15) with Microsoft SMTP Server (TLS) id 15.0.1156.6; Wed, 25 Jul 2018 14:27:35 -0500 Received: from linux-xvxi.natinst.com (130.164.49.7) by us-aus-exhub1.ni.corp.natinst.com (130.164.68.41) with Microsoft SMTP Server id 15.0.1156.6 via Frontend Transport; Wed, 25 Jul 2018 14:27:35 -0500 From: Joe Hershberger To: Date: Wed, 25 Jul 2018 14:25:30 -0500 Message-ID: <1532546732-11423-2-git-send-email-joe.hershberger@ni.com> X-Mailer: git-send-email 1.7.11.5 In-Reply-To: <1532546732-11423-1-git-send-email-joe.hershberger@ni.com> References: <1532546732-11423-1-git-send-email-joe.hershberger@ni.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-07-25_04:, , signatures=0 X-Proofpoint-Spam-Reason: safe Cc: Tom Rini , Sumit Garg , Heinrich Schuchardt , Alexander Graf , Joe Hershberger , Wenbin song Subject: [U-Boot] [PATCH 1/3] arm: Prevent redefinition error in fsl-layerscape X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The include/phy.h will start including dm.h, which pulls in linux/compat.h after the attempted redefinition in arch/arm/include/asm/armv8/mmu.h, so move this include to allow redefinition. Signed-off-by: Joe Hershberger --- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 40c2c3a..052e070 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -18,7 +19,6 @@ #include #include #include -#include #include #ifdef CONFIG_FSL_ESDHC #include