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[U-Boot,v2,01/16] arm: socfpga: stratix10: Add watchdog and firewall base addresses

Message ID 1526652336-34764-2-git-send-email-ley.foon.tan@intel.com
State Accepted
Commit 641f7470b66ad513c21ffd8113cca5eca09d1df5
Delegated to: Marek Vasut
Headers show
Series Add Intel Stratix 10 SoC support | expand

Commit Message

Ley Foon Tan May 18, 2018, 2:05 p.m. UTC 
Add the base address for watchdog and firewall.

Signed-off-by: Chin Liang See <chin.liang.see@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h |   11 +++++++++++
 1 files changed, 11 insertions(+), 0 deletions(-)
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Patch

diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
index 2c6e412..1f549d7 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
@@ -6,9 +6,11 @@ 
 #ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
 #define _SOCFPGA_S10_BASE_HARDWARE_H_
 
+#define SOCFPGA_CCU_ADDRESS			0xf7000000
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xf8000400
 #define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xf8010000
 #define SOCFPGA_SDR_ADDRESS			0xf8011000
+#define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS		0xf8020100
 #define SOCFPGA_SMMU_ADDRESS			0xfa000000
 #define SOCFPGA_MAILBOX_ADDRESS			0xffa30000
 #define SOCFPGA_UART0_ADDRESS			0xffc02000
@@ -17,12 +19,21 @@ 
 #define SOCFPGA_SPTIMER1_ADDRESS		0xffc03100
 #define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00000
 #define SOCFPGA_SYSTIMER1_ADDRESS		0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
+#define SOCFPGA_L4WD1_ADDRESS			0xffd00300
+#define SOCFPGA_L4WD2_ADDRESS			0xffd00400
+#define SOCFPGA_L4WD3_ADDRESS			0xffd00500
 #define SOCFPGA_GTIMER_SEC_ADDRESS		0xffd01000
 #define SOCFPGA_GTIMER_NSEC_ADDRESS		0xffd02000
 #define SOCFPGA_CLKMGR_ADDRESS			0xffd10000
 #define SOCFPGA_RSTMGR_ADDRESS			0xffd11000
 #define SOCFPGA_SYSMGR_ADDRESS			0xffd12000
 #define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd13000
+#define SOCFPGA_FIREWALL_L4_PER			0xffd21000
+#define SOCFPGA_FIREWALL_L4_SYS			0xffd21100
+#define SOCFPGA_FIREWALL_SOC2FPGA		0xffd21200
+#define SOCFPGA_FIREWALL_LWSOC2FPGA		0xffd21300
+#define SOCFPGA_FIREWALL_TCU			0xffd21400
 #define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
 #define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
 #define SOCFPGA_OCRAM_ADDRESS			0xffe00000