From patchwork Mon Apr 16 08:13:23 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick DELAUNAY X-Patchwork-Id: 898506 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 40Ph3t6MmBz9s0b for ; Mon, 16 Apr 2018 18:14:02 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 9E2AAC21D83; Mon, 16 Apr 2018 08:13:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1F024C21C27; Mon, 16 Apr 2018 08:13:53 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B1AD5C21C2C; Mon, 16 Apr 2018 08:13:51 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by lists.denx.de (Postfix) with ESMTPS id 65A88C21BE5 for ; Mon, 16 Apr 2018 08:13:51 +0000 (UTC) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w3G89JrN031018; Mon, 16 Apr 2018 10:13:49 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2hb6s69n2w-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 16 Apr 2018 10:13:49 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1F2B338; Mon, 16 Apr 2018 08:13:49 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 097EC1603; Mon, 16 Apr 2018 08:13:49 +0000 (GMT) Received: from SAFEX1HUBCAS22.st.com (10.75.90.93) by SAFEX1HUBCAS23.st.com (10.75.90.46) with Microsoft SMTP Server (TLS) id 14.3.361.1; Mon, 16 Apr 2018 10:13:49 +0200 Received: from localhost (10.201.23.85) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Mon, 16 Apr 2018 10:13:48 +0200 From: Patrick Delaunay To: Date: Mon, 16 Apr 2018 10:13:23 +0200 Message-ID: <1523866404-10884-2-git-send-email-patrick.delaunay@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1523866404-10884-1-git-send-email-patrick.delaunay@st.com> References: <1523866404-10884-1-git-send-email-patrick.delaunay@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.85] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-04-16_04:, , signatures=0 Cc: Tom Rini , Benjamin GAIGNARD Subject: [U-Boot] [PATCH v2 2/3] arm: psci: add a weak function psci_arch_cpu_entry X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The added function psci_arch_cpu_entry() is called during psci_cpu_entry() and can be used by arch to handle PSCI state transition from ON_PENDING to ON. The default weak function is empty: not behavior change. Signed-off-by: Patrick Delaunay --- Changes in v2: None arch/arm/cpu/armv7/psci.S | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm/cpu/armv7/psci.S b/arch/arm/cpu/armv7/psci.S index 35fd955..08b5088 100644 --- a/arch/arm/cpu/armv7/psci.S +++ b/arch/arm/cpu/armv7/psci.S @@ -321,11 +321,18 @@ ENTRY(psci_arch_init) ENDPROC(psci_arch_init) .weak psci_arch_init +ENTRY(psci_arch_cpu_entry) + mov pc, lr +ENDPROC(psci_arch_cpu_entry) +.weak psci_arch_cpu_entry + ENTRY(psci_cpu_entry) bl psci_enable_smp bl _nonsec_init + bl psci_arch_cpu_entry + bl psci_get_cpu_id @ CPU ID => r0 mov r2, r0 @ CPU ID => r2 bl psci_get_context_id @ context id => r0