diff mbox series

[U-Boot,25/36] rockchip: rk3288: prepare to use common board file

Message ID 1522142971-20739-26-git-send-email-kever.yang@rock-chips.com
State Changes Requested
Delegated to: Philipp Tomsich
Headers show
Series rockchip: clean up board file for rockchip SoCs | expand

Commit Message

Kever Yang March 27, 2018, 9:29 a.m. UTC
Use common board file and move SoC spec setting into rk3288.c

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
---

 arch/arm/mach-rockchip/rk3288-board-spl.c          | 304 ------------------
 arch/arm/mach-rockchip/rk3288-board-tpl.c          |  84 -----
 arch/arm/mach-rockchip/rk3288-board.c              | 338 ---------------------
 arch/arm/mach-rockchip/rk3288/rk3288.c             | 304 +++++++++++++++++-
 board/chipspark/popmetal_rk3288/popmetal-rk3288.c  |   9 +-
 board/mqmaker/miqi_rk3288/miqi-rk3288.c            |   7 -
 board/phytec/phycore_rk3288/phycore-rk3288.c       |  45 ++-
 board/rockchip/evb_rk3288/evb-rk3288.c             |   7 -
 .../rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c |   8 +
 board/rockchip/fennec_rk3288/fennec-rk3288.c       |   7 -
 board/rockchip/tinker_rk3288/tinker-rk3288.c       |   2 +-
 11 files changed, 357 insertions(+), 758 deletions(-)
 delete mode 100644 arch/arm/mach-rockchip/rk3288-board-spl.c
 delete mode 100644 arch/arm/mach-rockchip/rk3288-board-tpl.c
 delete mode 100644 arch/arm/mach-rockchip/rk3288-board.c
 create mode 100644 board/rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c

Comments

Philipp Tomsich April 1, 2018, 8:21 p.m. UTC | #1
> Use common board file and move SoC spec setting into rk3288.c
> 
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
> 
>  arch/arm/mach-rockchip/rk3288-board-spl.c          | 304 ------------------
>  arch/arm/mach-rockchip/rk3288-board-tpl.c          |  84 -----
>  arch/arm/mach-rockchip/rk3288-board.c              | 338 ---------------------
>  arch/arm/mach-rockchip/rk3288/rk3288.c             | 304 +++++++++++++++++-
>  board/chipspark/popmetal_rk3288/popmetal-rk3288.c  |   9 +-
>  board/mqmaker/miqi_rk3288/miqi-rk3288.c            |   7 -
>  board/phytec/phycore_rk3288/phycore-rk3288.c       |  45 ++-
>  board/rockchip/evb_rk3288/evb-rk3288.c             |   7 -
>  .../rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c |   8 +
>  board/rockchip/fennec_rk3288/fennec-rk3288.c       |   7 -
>  board/rockchip/tinker_rk3288/tinker-rk3288.c       |   2 +-
>  11 files changed, 357 insertions(+), 758 deletions(-)
>  delete mode 100644 arch/arm/mach-rockchip/rk3288-board-spl.c
>  delete mode 100644 arch/arm/mach-rockchip/rk3288-board-tpl.c
>  delete mode 100644 arch/arm/mach-rockchip/rk3288-board.c
>  create mode 100644 board/rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
diff mbox series

Patch

diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c
deleted file mode 100644
index f3ea624..0000000
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ /dev/null
@@ -1,304 +0,0 @@ 
-/*
- * (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <fdtdec.h>
-#include <i2c.h>
-#include <led.h>
-#include <malloc.h>
-#include <ram.h>
-#include <spl.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/bootrom.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pmu_rk3288.h>
-#include <asm/arch/sdram.h>
-#include <asm/arch/sdram_common.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/timer.h>
-#include <dm/pinctrl.h>
-#include <dm/root.h>
-#include <dm/test.h>
-#include <dm/util.h>
-#include <power/regulator.h>
-#include <power/rk8xx_pmic.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-u32 spl_boot_device(void)
-{
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
-	const void *blob = gd->fdt_blob;
-	struct udevice *dev;
-	const char *bootdev;
-	int node;
-	int ret;
-
-	bootdev = fdtdec_get_config_string(blob, "u-boot,boot0");
-	debug("Boot device %s\n", bootdev);
-	if (!bootdev)
-		goto fallback;
-
-	node = fdt_path_offset(blob, bootdev);
-	if (node < 0) {
-		debug("node=%d\n", node);
-		goto fallback;
-	}
-	ret = device_get_global_by_of_offset(node, &dev);
-	if (ret) {
-		debug("device at node %s/%d not found: %d\n", bootdev, node,
-		      ret);
-		goto fallback;
-	}
-	debug("Found device %s\n", dev->name);
-	switch (device_get_uclass_id(dev)) {
-	case UCLASS_SPI_FLASH:
-		return BOOT_DEVICE_SPI;
-	case UCLASS_MMC:
-		return BOOT_DEVICE_MMC1;
-	default:
-		debug("Booting from device uclass '%s' not supported\n",
-		      dev_get_uclass_name(dev));
-	}
-
-fallback:
-#elif defined(CONFIG_TARGET_CHROMEBOOK_JERRY) || \
-		defined(CONFIG_TARGET_CHROMEBIT_MICKEY) || \
-		defined(CONFIG_TARGET_CHROMEBOOK_MINNIE)
-	return BOOT_DEVICE_SPI;
-#endif
-	return BOOT_DEVICE_MMC1;
-}
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
-static int configure_emmc(struct udevice *pinctrl)
-{
-#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
-
-	struct gpio_desc desc;
-	int ret;
-
-	pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
-
-	/*
-	 * TODO(sjg@chromium.org): Pick this up from device tree or perhaps
-	 * use the EMMC_PWREN setting.
-	 */
-	ret = dm_gpio_lookup_name("D9", &desc);
-	if (ret) {
-		debug("gpio ret=%d\n", ret);
-		return ret;
-	}
-	ret = dm_gpio_request(&desc, "emmc_pwren");
-	if (ret) {
-		debug("gpio_request ret=%d\n", ret);
-		return ret;
-	}
-	ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
-	if (ret) {
-		debug("gpio dir ret=%d\n", ret);
-		return ret;
-	}
-	ret = dm_gpio_set_value(&desc, 1);
-	if (ret) {
-		debug("gpio value ret=%d\n", ret);
-		return ret;
-	}
-#endif
-	return 0;
-}
-#endif
-
-#if !defined(CONFIG_SPL_OF_PLATDATA)
-static int phycore_init(void)
-{
-	struct udevice *pmic;
-	int ret;
-
-	ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
-	if (ret)
-		return ret;
-
-#if defined(CONFIG_SPL_POWER_SUPPORT)
-	/* Increase USB input current to 2A */
-	ret = rk818_spl_configure_usb_input_current(pmic, 2000);
-	if (ret)
-		return ret;
-
-	/* Close charger when USB lower then 3.26V */
-	ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
-	if (ret)
-		return ret;
-#endif
-
-	return 0;
-}
-#endif
-
-void board_init_f(ulong dummy)
-{
-	struct udevice *pinctrl;
-	struct udevice *dev;
-	int ret;
-
-	/* Example code showing how to enable the debug UART on RK3288 */
-#include <asm/arch/grf_rk3288.h>
-	/* Enable early UART on the RK3288 */
-#define GRF_BASE	0xff770000
-	struct rk3288_grf * const grf = (void *)GRF_BASE;
-
-	rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
-		     GPIO7C6_MASK << GPIO7C6_SHIFT,
-		     GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
-		     GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
-	/*
-	 * Debug UART can be used from here if required:
-	 *
-	 * debug_uart_init();
-	 * printch('a');
-	 * printhex8(0x1234);
-	 * printascii("string");
-	 */
-	debug_uart_init();
-	debug("\nspl:debug uart enabled in %s\n", __func__);
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
-	rockchip_timer_init();
-	configure_l2ctlr();
-
-	ret = rockchip_get_clk(&dev);
-	if (ret) {
-		debug("CLK init failed: %d\n", ret);
-		return;
-	}
-
-	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
-	if (ret) {
-		debug("Pinctrl init failed: %d\n", ret);
-		return;
-	}
-
-#if !defined(CONFIG_SPL_OF_PLATDATA)
-	if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
-		ret = phycore_init();
-		if (ret) {
-			debug("Failed to set up phycore power settings: %d\n",
-			      ret);
-			return;
-		}
-	}
-#endif
-
-#if !defined(CONFIG_SUPPORT_TPL)
-	debug("\nspl:init dram\n");
-	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
-	if (ret) {
-		debug("DRAM init failed: %d\n", ret);
-		return;
-	}
-#endif
-
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT)
-	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-#endif
-}
-
-static int setup_led(void)
-{
-#ifdef CONFIG_SPL_LED
-	struct udevice *dev;
-	char *led_name;
-	int ret;
-
-	led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led");
-	if (!led_name)
-		return 0;
-	ret = led_get_by_label(led_name, &dev);
-	if (ret) {
-		debug("%s: get=%d\n", __func__, ret);
-		return ret;
-	}
-	ret = led_set_on(dev, 1);
-	if (ret)
-		return ret;
-#endif
-
-	return 0;
-}
-
-void spl_board_init(void)
-{
-	struct udevice *pinctrl;
-	int ret;
-
-	ret = setup_led();
-
-	if (ret) {
-		debug("LED ret=%d\n", ret);
-		hang();
-	}
-
-	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
-	if (ret) {
-		debug("%s: Cannot find pinctrl device\n", __func__);
-		goto err;
-	}
-
-#ifdef CONFIG_SPL_MMC_SUPPORT
-	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
-	if (ret) {
-		debug("%s: Failed to set up SD card\n", __func__);
-		goto err;
-	}
-	ret = configure_emmc(pinctrl);
-	if (ret) {
-		debug("%s: Failed to set up eMMC\n", __func__);
-		goto err;
-	}
-#endif
-
-	/* Enable debug UART */
-	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
-	if (ret) {
-		debug("%s: Failed to set up console UART\n", __func__);
-		goto err;
-	}
-
-	preloader_console_init();
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
-	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-#endif
-	return;
-err:
-	printf("spl_board_init: Error %d\n", ret);
-
-	/* No way to report error here */
-	hang();
-}
-
-#ifdef CONFIG_SPL_OS_BOOT
-
-#define PMU_BASE		0xff730000
-int dram_init_banksize(void)
-{
-	struct rk3288_pmu *const pmu = (void *)PMU_BASE;
-	size_t size = rockchip_sdram_size((phys_addr_t)&pmu->sys_reg[2]);
-
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = size;
-
-	return 0;
-}
-#endif
diff --git a/arch/arm/mach-rockchip/rk3288-board-tpl.c b/arch/arm/mach-rockchip/rk3288-board-tpl.c
deleted file mode 100644
index 150beea..0000000
--- a/arch/arm/mach-rockchip/rk3288-board-tpl.c
+++ /dev/null
@@ -1,84 +0,0 @@ 
-/*
- * Copyright (C) 2017 Amarula Solutions
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <debug_uart.h>
-#include <dm.h>
-#include <ram.h>
-#include <spl.h>
-#include <version.h>
-#include <asm/io.h>
-#include <asm/arch/bootrom.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/grf_rk3288.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pmu_rk3288.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/timer.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-#define GRF_BASE		0xff770000
-void board_init_f(ulong dummy)
-{
-	struct udevice *dev;
-	int ret;
-
-	/* Example code showing how to enable the debug UART on RK3288 */
-	/* Enable early UART on the RK3288 */
-	struct rk3288_grf * const grf = (void *)GRF_BASE;
-
-	rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
-		     GPIO7C6_MASK << GPIO7C6_SHIFT,
-		     GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
-		     GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
-	/*
-	 * Debug UART can be used from here if required:
-	 *
-	 * debug_uart_init();
-	 * printch('a');
-	 * printhex8(0x1234);
-	 * printascii("string");
-	 */
-	debug_uart_init();
-
-	ret = spl_early_init();
-	if (ret) {
-		debug("spl_early_init() failed: %d\n", ret);
-		hang();
-	}
-
-	rockchip_timer_init();
-	configure_l2ctlr();
-
-	ret = rockchip_get_clk(&dev);
-	if (ret) {
-		debug("CLK init failed: %d\n", ret);
-		return;
-	}
-
-	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
-	if (ret) {
-		debug("DRAM init failed: %d\n", ret);
-		return;
-	}
-}
-
-void board_return_to_bootrom(void)
-{
-	back_to_bootrom(BROM_BOOT_NEXTSTAGE);
-}
-
-u32 spl_boot_device(void)
-{
-	return BOOT_DEVICE_BOOTROM;
-}
-
-void spl_board_init(void)
-{
-	puts("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
-				U_BOOT_TIME ")\n");
-}
diff --git a/arch/arm/mach-rockchip/rk3288-board.c b/arch/arm/mach-rockchip/rk3288-board.c
deleted file mode 100644
index 1c53cca..0000000
--- a/arch/arm/mach-rockchip/rk3288-board.c
+++ /dev/null
@@ -1,338 +0,0 @@ 
-/*
- * (C) Copyright 2015 Google, Inc
- *
- * SPDX-License-Identifier:     GPL-2.0+
- */
-
-#include <common.h>
-#include <clk.h>
-#include <dm.h>
-#include <ram.h>
-#include <syscon.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/cru_rk3288.h>
-#include <asm/arch/periph.h>
-#include <asm/arch/pmu_rk3288.h>
-#include <asm/arch/qos_rk3288.h>
-#include <asm/arch/boot_mode.h>
-#include <asm/gpio.h>
-#include <dm/pinctrl.h>
-#include <dt-bindings/clock/rk3288-cru.h>
-#include <power/regulator.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-__weak int rk_board_late_init(void)
-{
-	return 0;
-}
-
-int rk3288_qos_init(void)
-{
-	int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
-	/* set vop qos to higher priority */
-	writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
-	writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
-
-	if (!fdt_node_check_compatible(gd->fdt_blob, 0,
-				       "rockchip,rk3288-tinker"))
-	{
-		/* set isp qos to higher priority */
-		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
-		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
-		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
-	}
-	return 0;
-}
-
-static void rk3288_detect_reset_reason(void)
-{
-	struct rk3288_cru *cru = rockchip_get_cru();
-	const char *reason;
-
-	if (IS_ERR(cru))
-		return;
-
-	switch (cru->cru_glb_rst_st) {
-	case GLB_POR_RST:
-		reason = "POR";
-		break;
-	case FST_GLB_RST_ST:
-	case SND_GLB_RST_ST:
-		reason = "RST";
-		break;
-	case FST_GLB_TSADC_RST_ST:
-	case SND_GLB_TSADC_RST_ST:
-		reason = "THERMAL";
-		break;
-	case FST_GLB_WDT_RST_ST:
-	case SND_GLB_WDT_RST_ST:
-		reason = "WDOG";
-		break;
-	default:
-		reason = "unknown reset";
-	}
-
-	env_set("reset_reason", reason);
-
-	/*
-	 * Clear cru_glb_rst_st, so we can determine the last reset cause
-	 * for following resets.
-	 */
-	rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
-}
-
-int board_late_init(void)
-{
-	setup_boot_mode();
-	rk3288_qos_init();
-	rk3288_detect_reset_reason();
-
-	return rk_board_late_init();
-}
-
-#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
-static int veyron_init(void)
-{
-	struct udevice *dev;
-	struct clk clk;
-	int ret;
-
-	ret = regulator_get_by_platname("vdd_arm", &dev);
-	if (ret) {
-		debug("Cannot set regulator name\n");
-		return ret;
-	}
-
-	/* Slowly raise to max CPU voltage to prevent overshoot */
-	ret = regulator_set_value(dev, 1200000);
-	if (ret)
-		return ret;
-	udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
-	ret = regulator_set_value(dev, 1400000);
-	if (ret)
-		return ret;
-	udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
-
-	ret = rockchip_get_clk(&clk.dev);
-	if (ret)
-		return ret;
-	clk.id = PLL_APLL;
-	ret = clk_set_rate(&clk, 1800000000);
-	if (IS_ERR_VALUE(ret))
-		return ret;
-
-	return 0;
-}
-#endif
-
-int board_init(void)
-{
-#if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
-	struct udevice *pinctrl;
-	int ret;
-
-	/*
-	 * We need to implement sdcard iomux here for the further
-	 * initlization, otherwise, it'll hit sdcard command sending
-	 * timeout exception.
-	 */
-	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
-	if (ret) {
-		debug("%s: Cannot find pinctrl device\n", __func__);
-		goto err;
-	}
-	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
-	if (ret) {
-		debug("%s: Failed to set up SD card\n", __func__);
-		goto err;
-	}
-
-	return 0;
-err:
-	printf("board_init: Error %d\n", ret);
-
-	/* No way to report error here */
-	hang();
-
-	return -1;
-#else
-	int ret;
-
-	/* We do some SoC one time setting here */
-	if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
-		ret = veyron_init();
-		if (ret)
-			return ret;
-	}
-
-	return 0;
-#endif
-}
-
-#ifndef CONFIG_SYS_DCACHE_OFF
-void enable_caches(void)
-{
-	/* Enable D-cache. I-cache is already enabled in start.S */
-	dcache_enable();
-}
-#endif
-
-#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
-#include <usb.h>
-#include <usb/dwc2_udc.h>
-
-static struct dwc2_plat_otg_data rk3288_otg_data = {
-	.rx_fifo_sz	= 512,
-	.np_tx_fifo_sz	= 16,
-	.tx_fifo_sz	= 128,
-};
-
-int board_usb_init(int index, enum usb_init_type init)
-{
-	int node, phy_node;
-	const char *mode;
-	bool matched = false;
-	const void *blob = gd->fdt_blob;
-	u32 grf_phy_offset;
-
-	/* find the usb_otg node */
-	node = fdt_node_offset_by_compatible(blob, -1,
-					"rockchip,rk3288-usb");
-
-	while (node > 0) {
-		mode = fdt_getprop(blob, node, "dr_mode", NULL);
-		if (mode && strcmp(mode, "otg") == 0) {
-			matched = true;
-			break;
-		}
-
-		node = fdt_node_offset_by_compatible(blob, node,
-					"rockchip,rk3288-usb");
-	}
-	if (!matched) {
-		debug("Not found usb_otg device\n");
-		return -ENODEV;
-	}
-	rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
-
-	node = fdtdec_lookup_phandle(blob, node, "phys");
-	if (node <= 0) {
-		debug("Not found usb phy device\n");
-		return -ENODEV;
-	}
-
-	phy_node = fdt_parent_offset(blob, node);
-	if (phy_node <= 0) {
-		debug("Not found usb phy device\n");
-		return -ENODEV;
-	}
-
-	rk3288_otg_data.phy_of_node = phy_node;
-	grf_phy_offset = fdtdec_get_addr(blob, node, "reg");
-
-	/* find the grf node */
-	node = fdt_node_offset_by_compatible(blob, -1,
-					"rockchip,rk3288-grf");
-	if (node <= 0) {
-		debug("Not found grf device\n");
-		return -ENODEV;
-	}
-	rk3288_otg_data.regs_phy = grf_phy_offset +
-				fdtdec_get_addr(blob, node, "reg");
-
-	return dwc2_udc_probe(&rk3288_otg_data);
-}
-
-int board_usb_cleanup(int index, enum usb_init_type init)
-{
-	return 0;
-}
-#endif
-
-static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
-		       char * const argv[])
-{
-	static const struct {
-		char *name;
-		int id;
-	} clks[] = {
-		{ "osc", CLK_OSC },
-		{ "apll", CLK_ARM },
-		{ "dpll", CLK_DDR },
-		{ "cpll", CLK_CODEC },
-		{ "gpll", CLK_GENERAL },
-#ifdef CONFIG_ROCKCHIP_RK3036
-		{ "mpll", CLK_NEW },
-#else
-		{ "npll", CLK_NEW },
-#endif
-	};
-	int ret, i;
-	struct udevice *dev;
-
-	ret = rockchip_get_clk(&dev);
-	if (ret) {
-		printf("clk-uclass not found\n");
-		return 0;
-	}
-
-	for (i = 0; i < ARRAY_SIZE(clks); i++) {
-		struct clk clk;
-		ulong rate;
-
-		clk.id = clks[i].id;
-		ret = clk_request(dev, &clk);
-		if (ret < 0)
-			continue;
-
-		rate = clk_get_rate(&clk);
-		printf("%s: %lu\n", clks[i].name, rate);
-
-		clk_free(&clk);
-	}
-
-	return 0;
-}
-
-U_BOOT_CMD(
-	clock, 2, 1, do_clock,
-	"display information about clocks",
-	""
-);
-
-#define GRF_SOC_CON2 0xff77024c
-
-int board_early_init_f(void)
-{
-	struct udevice *pinctrl;
-	struct udevice *dev;
-	int ret;
-
-	/*
-	 * This init is done in SPL, but when chain-loading U-Boot SPL will
-	 * have been skipped. Allow the clock driver to check if it needs
-	 * setting up.
-	 */
-	ret = rockchip_get_clk(&dev);
-	if (ret) {
-		debug("CLK init failed: %d\n", ret);
-		return ret;
-	}
-	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
-	if (ret) {
-		debug("%s: Cannot find pinctrl device\n", __func__);
-		return ret;
-	}
-
-	/* Enable debug UART */
-	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
-	if (ret) {
-		debug("%s: Failed to set up console UART\n", __func__);
-		return ret;
-	}
-	rk_setreg(GRF_SOC_CON2, 1 << 0);
-
-	return 0;
-}
diff --git a/arch/arm/mach-rockchip/rk3288/rk3288.c b/arch/arm/mach-rockchip/rk3288/rk3288.c
index 1e1c6be..0212015 100644
--- a/arch/arm/mach-rockchip/rk3288/rk3288.c
+++ b/arch/arm/mach-rockchip/rk3288/rk3288.c
@@ -3,11 +3,30 @@ 
  *
  * SPDX-License-Identifier:     GPL-2.0+
  */
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
 #include <asm/armv7.h>
 #include <asm/io.h>
+#include <asm/arch/bootrom.h>
+#include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/periph.h>
+#include <asm/arch/cru_rk3288.h>
+#include <asm/arch/grf_rk3288.h>
+#include <asm/arch/pmu_rk3288.h>
+#include <asm/arch/qos_rk3288.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+#include <dm/pinctrl.h>
+#include <dt-bindings/clock/rk3288-cru.h>
+#include <power/regulator.h>
 
-#define GRF_SOC_CON2 0xff77024c
+#define GRF_BASE               0xff770000
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+	[BROM_BOOTSOURCE_EMMC] = "/dwmmc@ff0f0000",
+	[BROM_BOOTSOURCE_SD] = "/dwmmc@ff0c0000",
+};
 
 #ifdef CONFIG_SPL_BUILD
 static void configure_l2ctlr(void)
@@ -36,7 +55,290 @@  int arch_cpu_init(void)
 #ifdef CONFIG_SPL_BUILD
 	configure_l2ctlr();
 #else
+	struct rk3288_grf * const grf = (void *)GRF_BASE;
+
 	/* Use rkpwm by default */
+	rk_setreg(&grf->soc_con2, 1 << 0);
+#endif
+	return 0;
+}
+
+void board_debug_uart_init(void)
+{
+	struct rk3288_grf * const grf = (void *)GRF_BASE;
+
+	rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT |
+		     GPIO7C6_MASK << GPIO7C6_SHIFT,
+		     GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT |
+		     GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT);
+}
+
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_TPL_BUILD)
+#ifdef CONFIG_SPL_MMC_SUPPORT
+static int configure_emmc(void)
+{
+#if defined(CONFIG_TARGET_CHROMEBOOK_JERRY)
+
+	struct gpio_desc desc;
+	int ret;
+	struct udevice *pinctrl;
+
+	pinctrl_request_noflags(pinctrl, PERIPH_ID_EMMC);
+
+	/*
+	 * TODO(sjg@chromium.org): Pick this up from device tree or perhaps
+	 * use the EMMC_PWREN setting.
+	 */
+	ret = dm_gpio_lookup_name("D9", &desc);
+	if (ret) {
+		debug("gpio ret=%d\n", ret);
+		return ret;
+	}
+	ret = dm_gpio_request(&desc, "emmc_pwren");
+	if (ret) {
+		debug("gpio_request ret=%d\n", ret);
+		return ret;
+	}
+	ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+	if (ret) {
+		debug("gpio dir ret=%d\n", ret);
+		return ret;
+	}
+	ret = dm_gpio_set_value(&desc, 1);
+	if (ret) {
+		debug("gpio value ret=%d\n", ret);
+		return ret;
+	}
+#endif
+	return 0;
+}
+
+int rk_spl_board_init(void)
+{
+	struct udevice *pinctrl;
+	int ret = 0;
+
+	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+	if (ret) {
+		debug("%s: Cannot find pinctrl device\n", __func__);
+		goto err;
+	}
+	/* TODO: we may need to check boot device first */
+#ifdef CONFIG_SPL_MMC_SUPPORT
+	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD);
+	if (ret) {
+		debug("%s: Failed to set up SD card\n", __func__);
+		goto err;
+	}
+#endif
+
+	ret = configure_emmc();
+	if (ret)
+		debug("%s: Failed to set up eMMC\n", __func__);
+
+err:
+	return ret;
+}
+#endif
+#endif
+
+int rk3288_qos_init(void)
+{
+	int val = 2 << PRIORITY_HIGH_SHIFT | 2 << PRIORITY_LOW_SHIFT;
+	/* set vop qos to higher priority */
+	writel(val, CPU_AXI_QOS_PRIORITY + VIO0_VOP_QOS);
+	writel(val, CPU_AXI_QOS_PRIORITY + VIO1_VOP_QOS);
+
+	if (!fdt_node_check_compatible(gd->fdt_blob, 0,
+				       "rockchip,rk3288-tinker")) {
+		/* set isp qos to higher priority */
+		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_R_QOS);
+		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W0_QOS);
+		writel(val, CPU_AXI_QOS_PRIORITY + VIO1_ISP_W1_QOS);
+	}
+	return 0;
+}
+
+static void rk3288_detect_reset_reason(void)
+{
+	struct rk3288_cru *cru = rockchip_get_cru();
+	const char *reason;
+
+	if (IS_ERR(cru))
+		return;
+
+	switch (cru->cru_glb_rst_st) {
+	case GLB_POR_RST:
+		reason = "POR";
+		break;
+	case FST_GLB_RST_ST:
+	case SND_GLB_RST_ST:
+		reason = "RST";
+		break;
+	case FST_GLB_TSADC_RST_ST:
+	case SND_GLB_TSADC_RST_ST:
+		reason = "THERMAL";
+		break;
+	case FST_GLB_WDT_RST_ST:
+	case SND_GLB_WDT_RST_ST:
+		reason = "WDOG";
+		break;
+	default:
+		reason = "unknown reset";
+	}
+
+	env_set("reset_reason", reason);
+
+	/*
+	 * Clear cru_glb_rst_st, so we can determine the last reset cause
+	 * for following resets.
+	 */
+	rk_clrreg(&cru->cru_glb_rst_st, GLB_RST_ST_MASK);
+}
+
+__weak int rk3288_board_late_init(void)
+{
+	return 0;
+}
+
+int rk_board_late_init(void)
+{
+	rk3288_qos_init();
+	rk3288_detect_reset_reason();
+
+	return rk3288_board_late_init();
+}
+
+#if !CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM)
+static int veyron_init(void)
+{
+	struct udevice *dev;
+	struct clk clk;
+	int ret;
+
+	ret = regulator_get_by_platname("vdd_arm", &dev);
+	if (ret) {
+		debug("Cannot set regulator name\n");
+		return ret;
+	}
+
+	/* Slowly raise to max CPU voltage to prevent overshoot */
+	ret = regulator_set_value(dev, 1200000);
+	if (ret)
+		return ret;
+	udelay(175); /* Must wait for voltage to stabilize, 2mV/us */
+	ret = regulator_set_value(dev, 1400000);
+	if (ret)
+		return ret;
+	udelay(100); /* Must wait for voltage to stabilize, 2mV/us */
+
+	ret = rockchip_get_clk(&clk.dev);
+	if (ret)
+		return ret;
+	clk.id = PLL_APLL;
+	ret = clk_set_rate(&clk, 1800000000);
+	if (IS_ERR_VALUE(ret))
+		return ret;
+
+	return 0;
+}
+
+int rk_board_init(void)
+{
+	int ret;
+
+	/* We do some SoC one time setting here */
+	if (!fdt_node_check_compatible(gd->fdt_blob, 0, "google,veyron")) {
+		ret = veyron_init();
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+#endif
+
+static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
+		    char * const argv[])
+{
+	static const struct {
+		char *name;
+		int id;
+	} clks[] = {
+		{ "osc", CLK_OSC },
+		{ "apll", CLK_ARM },
+		{ "dpll", CLK_DDR },
+		{ "cpll", CLK_CODEC },
+		{ "gpll", CLK_GENERAL },
+#ifdef CONFIG_ROCKCHIP_RK3036
+		{ "mpll", CLK_NEW },
+#else
+		{ "npll", CLK_NEW },
+#endif
+	};
+	int ret, i;
+	struct udevice *dev;
+
+	ret = rockchip_get_clk(&dev);
+	if (ret) {
+		printf("clk-uclass not found\n");
+		return 0;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(clks); i++) {
+		struct clk clk;
+		ulong rate;
+
+		clk.id = clks[i].id;
+		ret = clk_request(dev, &clk);
+		if (ret < 0)
+			continue;
+
+		rate = clk_get_rate(&clk);
+		printf("%s: %lu\n", clks[i].name, rate);
+
+		clk_free(&clk);
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	clock, 2, 1, do_clock,
+	"display information about clocks",
+	""
+);
+
+#define GRF_SOC_CON2 0xff77024c
+
+int board_early_init_f(void)
+{
+	struct udevice *pinctrl;
+	struct udevice *dev;
+	int ret;
+
+	/*
+	 * This init is done in SPL, but when chain-loading U-Boot SPL will
+	 * have been skipped. Allow the clock driver to check if it needs
+	 * setting up.
+	 */
+	ret = rockchip_get_clk(&dev);
+	if (ret) {
+		debug("CLK init failed: %d\n", ret);
+		return ret;
+	}
+	ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
+	if (ret) {
+		debug("%s: Cannot find pinctrl device\n", __func__);
+		return ret;
+	}
+
+	/* Enable debug UART */
+	ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG);
+	if (ret) {
+		debug("%s: Failed to set up console UART\n", __func__);
+		return ret;
+	}
 	rk_setreg(GRF_SOC_CON2, 1 << 0);
 
 	return 0;
diff --git a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
index ed82b2b..9945f97 100644
--- a/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
+++ b/board/chipspark/popmetal_rk3288/popmetal-rk3288.c
@@ -8,16 +8,9 @@ 
 #include <spl.h>
 #include <asm/gpio.h>
 
-void board_boot_order(u32 *spl_boot_list)
-{
-	/* eMMC prior to sdcard */
-	spl_boot_list[0] = BOOT_DEVICE_MMC2;
-	spl_boot_list[1] = BOOT_DEVICE_MMC1;
-}
-
 #define GPIO7A3_HUB_RST	227
 
-int rk_board_late_init(void)
+int rk3288_board_late_init(void)
 {
 	int ret;
 
diff --git a/board/mqmaker/miqi_rk3288/miqi-rk3288.c b/board/mqmaker/miqi_rk3288/miqi-rk3288.c
index a82f0ae..846dedd 100644
--- a/board/mqmaker/miqi_rk3288/miqi-rk3288.c
+++ b/board/mqmaker/miqi_rk3288/miqi-rk3288.c
@@ -6,10 +6,3 @@ 
 
 #include <common.h>
 #include <spl.h>
-
-void board_boot_order(u32 *spl_boot_list)
-{
-	/* eMMC prior to sdcard. */
-	spl_boot_list[0] = BOOT_DEVICE_MMC2;
-	spl_boot_list[1] = BOOT_DEVICE_MMC1;
-}
diff --git a/board/phytec/phycore_rk3288/phycore-rk3288.c b/board/phytec/phycore_rk3288/phycore-rk3288.c
index 47b069e..175c017 100644
--- a/board/phytec/phycore_rk3288/phycore-rk3288.c
+++ b/board/phytec/phycore_rk3288/phycore-rk3288.c
@@ -12,6 +12,7 @@ 
 #include <i2c_eeprom.h>
 #include <netdev.h>
 #include "som.h"
+#include <power/rk8xx_pmic.h>
 
 static int valid_rk3288_som(struct rk3288_som *som)
 {
@@ -27,7 +28,49 @@  static int valid_rk3288_som(struct rk3288_som *som)
 	return hw == som->bs;
 }
 
-int rk_board_late_init(void)
+#if defined(CONFIG_SPL_BUILD) && !defined(CONFIG_SPL_OF_PLATDATA)
+static int phycore_init(void)
+{
+	struct udevice *pmic;
+	int ret;
+
+	ret = uclass_first_device_err(UCLASS_PMIC, &pmic);
+	if (ret)
+		return ret;
+
+#if defined(CONFIG_SPL_POWER_SUPPORT)
+	/* Increase USB input current to 2A */
+	ret = rk818_spl_configure_usb_input_current(pmic, 2000);
+	if (ret)
+		return ret;
+
+	/* Close charger when USB lower then 3.26V */
+	ret = rk818_spl_configure_usb_chrg_shutdown(pmic, 3260000);
+	if (ret)
+		return ret;
+#endif
+
+	return 0;
+}
+
+int rk_board_init_f(void)
+{
+	int ret = 0;
+
+	if (of_machine_is_compatible("phytec,rk3288-phycore-som")) {
+		ret = phycore_init();
+		if (ret) {
+			debug("Failed to set up phycore power settings: %d\n",
+			      ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+#endif
+
+int rk3288_board_late_init(void)
 {
 	int ret;
 	struct udevice *dev;
diff --git a/board/rockchip/evb_rk3288/evb-rk3288.c b/board/rockchip/evb_rk3288/evb-rk3288.c
index a82f0ae..846dedd 100644
--- a/board/rockchip/evb_rk3288/evb-rk3288.c
+++ b/board/rockchip/evb_rk3288/evb-rk3288.c
@@ -6,10 +6,3 @@ 
 
 #include <common.h>
 #include <spl.h>
-
-void board_boot_order(u32 *spl_boot_list)
-{
-	/* eMMC prior to sdcard. */
-	spl_boot_list[0] = BOOT_DEVICE_MMC2;
-	spl_boot_list[1] = BOOT_DEVICE_MMC1;
-}
diff --git a/board/rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c b/board/rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c
new file mode 100644
index 0000000..88b6327
--- /dev/null
+++ b/board/rockchip/evb_rk3288_rk1608/evb-rk3288-rk1608.c
@@ -0,0 +1,8 @@ 
+/*
+ * (C) Copyright 2017 Rockchip Electronics Co., Ltd
+ *
+ * SPDX-License-Identifier:     GPL-2.0+
+ */
+
+#include <common.h>
+#include <spl.h>
diff --git a/board/rockchip/fennec_rk3288/fennec-rk3288.c b/board/rockchip/fennec_rk3288/fennec-rk3288.c
index aad74ef..846dedd 100644
--- a/board/rockchip/fennec_rk3288/fennec-rk3288.c
+++ b/board/rockchip/fennec_rk3288/fennec-rk3288.c
@@ -6,10 +6,3 @@ 
 
 #include <common.h>
 #include <spl.h>
-
-void board_boot_order(u32 *spl_boot_list)
-{
-	/* eMMC prior to sdcard */
-	spl_boot_list[0] = BOOT_DEVICE_MMC2;
-	spl_boot_list[1] = BOOT_DEVICE_MMC1;
-}
diff --git a/board/rockchip/tinker_rk3288/tinker-rk3288.c b/board/rockchip/tinker_rk3288/tinker-rk3288.c
index 790a921..5681ef1 100644
--- a/board/rockchip/tinker_rk3288/tinker-rk3288.c
+++ b/board/rockchip/tinker_rk3288/tinker-rk3288.c
@@ -21,7 +21,7 @@  static int get_ethaddr_from_eeprom(u8 *addr)
 	return i2c_eeprom_read(dev, 0, addr, 6);
 }
 
-int rk_board_late_init(void)
+int rk3288_board_late_init(void)
 {
 	u8 ethaddr[6];