From patchwork Tue Mar 27 09:29:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kever Yang X-Patchwork-Id: 891460 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rock-chips.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="LxxGvcSU"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 409QpK2Jq3z9s1S for ; Tue, 27 Mar 2018 20:34:48 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B00ECC22095; Tue, 27 Mar 2018 09:32:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 68F69C21FBA; Tue, 27 Mar 2018 09:30:56 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 77A09C21F1B; Tue, 27 Mar 2018 09:30:18 +0000 (UTC) Received: from mail-pg0-f65.google.com (mail-pg0-f65.google.com [74.125.83.65]) by lists.denx.de (Postfix) with ESMTPS id 565D9C21FAB for ; Tue, 27 Mar 2018 09:30:14 +0000 (UTC) Received: by mail-pg0-f65.google.com with SMTP id n11so8344045pgp.4 for ; Tue, 27 Mar 2018 02:30:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=SxAqimND9N4ot3K/DD4JjObXhofYlXxZfFWSCBh3fmw=; b=LxxGvcSUX0klrnDgRpcUkHAOfAggBaDibZhw8OybTqRLk3ekUAvOcCsa0zd+yqVN90 HiEARt0VPA7iZ/Z2BFFQhGX+kCmNoSYeas08chIfi5f1gbsUHgLYahzfSTc2bvW03Ru9 zOU3rMjoN6vCizozislKzQlf5wuNd8Dy9yVEha/fASL27ZoDkajA9rfLL8H2M91t4183 HF7ooZ8of22PX7tPuV4OUvwiyLs+07l9/AAZ2WtSbP3Rk6XHfWbzNy3JatscszYK1v5c tt6vJ7W5LJfZqGJsBEFE8voHWYSSc6/X2T5dGZUUhgIf1oCItBEu7i5lriTkqa3Nw94f EQvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=SxAqimND9N4ot3K/DD4JjObXhofYlXxZfFWSCBh3fmw=; b=KWklVaJi26ukWX1CRHbeXpEylpUTnrMMxdbH6KY7cBGNwCeK9BNq28/zwMKEBGxw4H lGpIRjWn6vur+F+fhZsqGO+muvbIgr/OBMZWtt89NpqSi+lWLbBaZtYYRj9xB5ZqayQE gOrnXlpVEZaYBENb7IDLNhn2PGc1LSFiUsBoYmxh4EdSMj4UuJ/yUMfitb0v62AJQOej Z2brOni43MEQhoa7Szq+0GS5XvZVHRsmotMidhbzS0d3c503eiQEsWWgBg6vC5n8PFsC qTiSSYhwlvx4cUVZuiQaQsQST2UriXufmF9S67k39L+fN1fiuZQGaPCyukh97qpCZNAI 5ikQ== X-Gm-Message-State: AElRT7FEu1jGgwRgN+j323v6F9eBoU5cOVtterXZnLyyZcxNmG3YQeUH Qz2zh0TnrgwzIxEK/mSEBlPXKQ== X-Google-Smtp-Source: AG47ELsEktVgXWTq2h++rtwUsFBUVWsDCgyQLQtcVHT6N6Zn8bul/vdkdktBI25tqHCe6y9+aFFsWw== X-Received: by 10.99.96.19 with SMTP id u19mr30098983pgb.261.1522143012457; Tue, 27 Mar 2018 02:30:12 -0700 (PDT) Received: from localhost.localdomain ([103.29.142.67]) by smtp.gmail.com with ESMTPSA id j83sm2171561pfj.18.2018.03.27.02.30.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 27 Mar 2018 02:30:11 -0700 (PDT) From: Kever Yang To: u-boot@lists.denx.de Date: Tue, 27 Mar 2018 17:29:03 +0800 Message-Id: <1522142971-20739-10-git-send-email-kever.yang@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> References: <1522142971-20739-1-git-send-email-kever.yang@rock-chips.com> Subject: [U-Boot] [PATCH 09/36] rockchip: rk322x: sdram: use common udelay instead of rockchip_udelay X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Do not need to use rockchip_udelay after we can use systimer. Signed-off-by: Kever Yang Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- drivers/ram/rockchip/sdram_rk322x.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/drivers/ram/rockchip/sdram_rk322x.c b/drivers/ram/rockchip/sdram_rk322x.c index cc3138b..c4da000 100644 --- a/drivers/ram/rockchip/sdram_rk322x.c +++ b/drivers/ram/rockchip/sdram_rk322x.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -97,26 +96,26 @@ void phy_pctrl_reset(struct rk322x_cru *cru, 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT | 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT); - rockchip_udelay(10); + udelay(10); rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRPHY_PSRST_SHIFT | 1 << DDRPHY_SRST_SHIFT); - rockchip_udelay(10); + udelay(10); rk_clrreg(&cru->cru_softrst_con[5], 1 << DDRCTRL_PSRST_SHIFT | 1 << DDRCTRL_SRST_SHIFT); - rockchip_udelay(10); + udelay(10); clrbits_le32(&ddr_phy->ddrphy_reg[0], SOFT_RESET_MASK << SOFT_RESET_SHIFT); - rockchip_udelay(10); + udelay(10); setbits_le32(&ddr_phy->ddrphy_reg[0], SOFT_DERESET_ANALOG); - rockchip_udelay(5); + udelay(5); setbits_le32(&ddr_phy->ddrphy_reg[0], SOFT_DERESET_DIGITAL); - rockchip_udelay(1); + udelay(1); } void phy_dll_bypass_set(struct rk322x_ddr_phy *ddr_phy, u32 freq) @@ -155,7 +154,7 @@ static void send_command(struct rk322x_ddr_pctl *pctl, u32 rank, u32 cmd, u32 arg) { writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); - rockchip_udelay(1); + udelay(1); while (readl(&pctl->mcmd) & START_CMD) ; } @@ -168,7 +167,7 @@ static void memory_init(struct chan_info *chan, if (dramtype == DDR3) { send_command(pctl, 3, DESELECT_CMD, 0); - rockchip_udelay(1); + udelay(1); send_command(pctl, 3, PREA_CMD, 0); send_command(pctl, 3, MRS_CMD, (0x02 & BANK_ADDR_MASK) << BANK_ADDR_SHIFT | @@ -197,17 +196,17 @@ static void memory_init(struct chan_info *chan, (0x63 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | (0 & LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); - rockchip_udelay(10); + udelay(10); send_command(pctl, 3, MRS_CMD, (0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | (0xff & LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); - rockchip_udelay(1); + udelay(1); send_command(pctl, 3, MRS_CMD, (0x10 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | (0xff & LPDDR23_OP_MASK) << LPDDR23_OP_SHIFT); - rockchip_udelay(1); + udelay(1); send_command(pctl, 3, MRS_CMD, (1 & LPDDR23_MA_MASK) << LPDDR23_MA_SHIFT | (sdram_params->phy_timing.mr[1] & @@ -244,7 +243,7 @@ static u32 data_training(struct chan_info *chan) DQS_SQU_CAL_SEL_CS0); setbits_le32(&ddr_phy->ddrphy_reg[2], DQS_SQU_CAL_START); - rockchip_udelay(30); + udelay(30); ret = readl(&ddr_phy->ddrphy_reg[0xff]); clrbits_le32(&ddr_phy->ddrphy_reg[2], @@ -368,9 +367,9 @@ static void phy_softreset(struct dram_info *dram) writel(GRF_DDRPHY_BUFFEREN_CORE_EN, &grf->soc_con[0]); clrbits_le32(&ddr_phy->ddrphy_reg[0], 0x3 << 2); - rockchip_udelay(1); + udelay(1); setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 2); - rockchip_udelay(5); + udelay(5); setbits_le32(&ddr_phy->ddrphy_reg[0], 1 << 3); writel(GRF_DDRPHY_BUFFEREN_CORE_DIS, &grf->soc_con[0]); }