From patchwork Tue Mar 20 10:41:25 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Patrick DELAUNAY X-Patchwork-Id: 888154 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4058fT4jC0z9sX0 for ; Tue, 20 Mar 2018 21:43:13 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 37FD7C21D8A; Tue, 20 Mar 2018 10:43:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id D872CC21CB1; Tue, 20 Mar 2018 10:43:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E6D47C21D65; Tue, 20 Mar 2018 10:43:01 +0000 (UTC) Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [62.209.51.94]) by lists.denx.de (Postfix) with ESMTPS id 9E943C21CB1 for ; Tue, 20 Mar 2018 10:43:01 +0000 (UTC) Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w2KAdWs3027841; Tue, 20 Mar 2018 11:43:00 +0100 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2grsc1yg18-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 20 Mar 2018 11:43:00 +0100 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5136F34; Tue, 20 Mar 2018 10:43:00 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas21.st.com [10.75.90.44]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 2134325C2; Tue, 20 Mar 2018 10:43:00 +0000 (GMT) Received: from SAFEX1HUBCAS23.st.com (10.75.90.47) by SAFEX1HUBCAS21.st.com (10.75.90.44) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 20 Mar 2018 11:43:00 +0100 Received: from localhost (10.201.23.85) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Tue, 20 Mar 2018 11:42:59 +0100 From: Patrick Delaunay To: Date: Tue, 20 Mar 2018 11:41:25 +0100 Message-ID: <1521542486-4827-3-git-send-email-patrick.delaunay@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1521542486-4827-1-git-send-email-patrick.delaunay@st.com> References: <1521542486-4827-1-git-send-email-patrick.delaunay@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.85] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2018-03-20_05:, , signatures=0 Cc: Tom Rini , Benjamin GAIGNARD Subject: [U-Boot] [PATCH 3/4] clock: stm32mp1: add stgen clock source change support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The STGEN is the clock source for the Cortex A7 arch timer. So after modification of its frequency, CP15 cntfreq is updated and a new timer init is performed. Signed-off-by: Patrick Delaunay --- drivers/clk/clk_stm32mp1.c | 46 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c index 55b0f79..c67aa44 100644 --- a/drivers/clk/clk_stm32mp1.c +++ b/drivers/clk/clk_stm32mp1.c @@ -27,6 +27,15 @@ #define TIMEOUT_200MS 200000 #define TIMEOUT_1S 1000000 +/* STGEN registers */ +#define STGENC_CNTCR 0x00 +#define STGENC_CNTSR 0x04 +#define STGENC_CNTCVL 0x08 +#define STGENC_CNTCVU 0x0C +#define STGENC_CNTFID0 0x20 + +#define STGENC_CNTCR_EN BIT(0) + /* RCC registers */ #define RCC_OCENSETR 0x0C #define RCC_OCENCLRR 0x10 @@ -1377,6 +1386,36 @@ static int set_clksrc(struct stm32mp1_clk_priv *priv, unsigned int clksrc) return ret; } +static void stgen_config(struct stm32mp1_clk_priv *priv) +{ + int p; + u32 stgenc, cntfid0; + ulong rate; + + stgenc = (u32)syscon_get_first_range(STM32MP_SYSCON_STGEN); + + cntfid0 = readl(stgenc + STGENC_CNTFID0); + p = stm32mp1_clk_get_parent(priv, STGEN_K); + rate = stm32mp1_clk_get(priv, p); + + if (cntfid0 != rate) { + pr_debug("System Generic Counter (STGEN) update\n"); + clrbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN); + writel(0x0, stgenc + STGENC_CNTCVL); + writel(0x0, stgenc + STGENC_CNTCVU); + writel(rate, stgenc + STGENC_CNTFID0); + setbits_le32(stgenc + STGENC_CNTCR, STGENC_CNTCR_EN); + + __asm__ volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (rate)); + + /* need to update gd->arch.timer_rate_hz with new frequency */ + timer_init(); + pr_debug("gd->arch.timer_rate_hz = %x\n", + (u32)gd->arch.timer_rate_hz); + pr_debug("Tick = %x\n", (u32)(get_ticks())); + } +} + static int set_clkdiv(unsigned int clkdiv, u32 address) { u32 val; @@ -1544,8 +1583,10 @@ static int stm32mp1_clktree(struct udevice *dev) /* configure HSIDIV */ debug("configure HSIDIV\n"); - if (priv->osc[_HSI]) + if (priv->osc[_HSI]) { stm32mp1_hsidiv(rcc, priv->osc[_HSI]); + stgen_config(priv); + } /* select DIV */ debug("select DIV\n"); @@ -1634,6 +1675,9 @@ static int stm32mp1_clktree(struct udevice *dev) pkcs_config(priv, CLK_CKPER_DISABLED); } + /* STGEN clock source can change with CLK_STGEN_XXX */ + stgen_config(priv); + debug("oscillator off\n"); /* switch OFF HSI if not found in device-tree */ if (!priv->osc[_HSI])