From patchwork Sat Feb 3 12:16:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 868890 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zYXxY4RZNz9t5s for ; Sat, 3 Feb 2018 23:20:33 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 3D605C21E26; Sat, 3 Feb 2018 12:18:04 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_DNSWL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 27062C21E45; Sat, 3 Feb 2018 12:17:16 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 3439FC21E39; Sat, 3 Feb 2018 12:17:07 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.137]) by lists.denx.de (Postfix) with ESMTPS id BFA9FC21E35 for ; Sat, 3 Feb 2018 12:17:01 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.78]) by regular1.263xmail.com (Postfix) with ESMTP id 4335DDAC4; Sat, 3 Feb 2018 20:16:56 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id C976A381; Sat, 3 Feb 2018 20:16:57 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 220.200.40.59 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <58ac5587ff3d87cfdd83ce43d59f313a> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [220.200.40.59]) by smtp.263.net (Postfix) whith SMTP id 6626RH04OX; Sat, 03 Feb 2018 20:16:58 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com Date: Sat, 3 Feb 2018 20:16:36 +0800 Message-Id: <1517660196-21802-5-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> References: <1517660196-21802-1-git-send-email-david.wu@rock-chips.com> Cc: u-boot@lists.denx.de, David Wu Subject: [U-Boot] [PATCH 04/14] net: rockchip: Add integrated phy for rk3228 and rk3328 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The rk3228 and rk3328 Socs both support integrated phy, implement their power up function to support it. Signed-off-by: David Wu Acked-by: Philipp Tomsich --- drivers/net/gmac_rockchip.c | 122 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index bca0a2a..ec47933 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -583,6 +583,126 @@ static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) RV1108_GMAC_PHY_INTF_SEL_RMII); } +static void rk3228_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) +{ + struct rk322x_grf *grf; + enum { + RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK = BIT(15), + RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY = BIT(15), + }; + enum { + RK3228_MACPHY_CFG_CLK_50M_MASK = BIT(14), + RK3228_MACPHY_CFG_CLK_50M = BIT(14), + + RK3228_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), + RK3228_MACPHY_RMII_MODE = BIT(6), + + RK3228_MACPHY_ENABLE_MASK = BIT(0), + RK3228_MACPHY_DISENABLE = 0, + RK3228_MACPHY_ENABLE = BIT(0), + }; + enum { + RK3228_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), + RK3228_RK_GRF_CON2_MACPHY_ID = 0x1234, + }; + enum { + RK3228_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), + RK3228_RK_GRF_CON3_MACPHY_ID = 0x35, + }; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->con_iomux, + RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY_MASK, + RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); + + rk_clrsetreg(&grf->macphy_con[2], + RK3228_RK_GRF_CON2_MACPHY_ID_MASK, + RK3228_RK_GRF_CON2_MACPHY_ID); + + rk_clrsetreg(&grf->macphy_con[3], + RK3228_RK_GRF_CON3_MACPHY_ID_MASK, + RK3228_RK_GRF_CON3_MACPHY_ID); + + /* disabled before trying to reset it &*/ + rk_clrsetreg(&grf->macphy_con[0], + RK3228_MACPHY_CFG_CLK_50M_MASK | + RK3228_MACPHY_RMII_MODE_MASK | + RK3228_MACPHY_ENABLE_MASK, + RK3228_MACPHY_CFG_CLK_50M | + RK3228_MACPHY_RMII_MODE | + RK3228_MACPHY_DISENABLE); + + reset_assert(&pdata->phy_reset); + udelay(10); + reset_deassert(&pdata->phy_reset); + udelay(10); + + rk_clrsetreg(&grf->macphy_con[0], + RK3228_MACPHY_ENABLE_MASK, + RK3228_MACPHY_ENABLE); + udelay(30 * 1000); +} + +static void rk3328_gmac_integrated_phy_powerup(struct gmac_rockchip_platdata *pdata) +{ + struct rk3328_grf_regs *grf; + enum { + RK3328_GRF_CON_RMII_MODE_MASK = BIT(9), + RK3328_GRF_CON_RMII_MODE = BIT(9), + }; + enum { + RK3328_MACPHY_CFG_CLK_50M_MASK = BIT(14), + RK3328_MACPHY_CFG_CLK_50M = BIT(14), + + RK3328_MACPHY_RMII_MODE_MASK = GENMASK(7, 6), + RK3328_MACPHY_RMII_MODE = BIT(6), + + RK3328_MACPHY_ENABLE_MASK = BIT(0), + RK3328_MACPHY_DISENABLE = 0, + RK3328_MACPHY_ENABLE = BIT(0), + }; + enum { + RK3328_RK_GRF_CON2_MACPHY_ID_MASK = GENMASK(6, 0), + RK3328_RK_GRF_CON2_MACPHY_ID = 0x1234, + }; + enum { + RK3328_RK_GRF_CON3_MACPHY_ID_MASK = GENMASK(5, 0), + RK3328_RK_GRF_CON3_MACPHY_ID = 0x35, + }; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->macphy_con[1], + RK3328_GRF_CON_RMII_MODE_MASK, + RK3328_GRF_CON_RMII_MODE); + + rk_clrsetreg(&grf->macphy_con[2], + RK3328_RK_GRF_CON2_MACPHY_ID_MASK, + RK3328_RK_GRF_CON2_MACPHY_ID); + + rk_clrsetreg(&grf->macphy_con[3], + RK3328_RK_GRF_CON3_MACPHY_ID_MASK, + RK3328_RK_GRF_CON3_MACPHY_ID); + + /* disabled before trying to reset it &*/ + rk_clrsetreg(&grf->macphy_con[0], + RK3328_MACPHY_CFG_CLK_50M_MASK | + RK3328_MACPHY_RMII_MODE_MASK | + RK3328_MACPHY_ENABLE_MASK, + RK3328_MACPHY_CFG_CLK_50M | + RK3328_MACPHY_RMII_MODE | + RK3328_MACPHY_DISENABLE); + + reset_assert(&pdata->phy_reset); + udelay(10); + reset_deassert(&pdata->phy_reset); + udelay(10); + + rk_clrsetreg(&grf->macphy_con[0], + RK3328_MACPHY_ENABLE_MASK, + RK3328_MACPHY_ENABLE); + udelay(30 * 1000); +} + static int gmac_rockchip_probe(struct udevice *dev) { struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); @@ -695,6 +815,7 @@ const struct rk_gmac_ops rk3228_gmac_ops = { .fix_rgmii_speed = rk3228_gmac_fix_rgmii_speed, .set_to_rmii = rk3228_gmac_set_to_rmii, .set_to_rgmii = rk3228_gmac_set_to_rgmii, + .integrated_phy_powerup = rk3228_gmac_integrated_phy_powerup, }; const struct rk_gmac_ops rk3288_gmac_ops = { @@ -707,6 +828,7 @@ const struct rk_gmac_ops rk3328_gmac_ops = { .fix_rgmii_speed = rk3328_gmac_fix_rgmii_speed, .set_to_rmii = rk3328_gmac_set_to_rmii, .set_to_rgmii = rk3328_gmac_set_to_rgmii, + .integrated_phy_powerup = rk3328_gmac_integrated_phy_powerup, }; const struct rk_gmac_ops rk3368_gmac_ops = {