| Message ID | 1515823576-53032-1-git-send-email-david.wu@rock-chips.com |
|---|---|
| State | Accepted |
| Commit | c513e9e1e6e1ea2aa177aae3b0eb306c949dcd69 |
| Delegated to: | Philipp Tomsich |
| Headers | show |
| Series | Add gmac support for rk3399-evb rv1108-evb rk3328-evb and rk3229-evb | expand |
> The LCDC assigned rate is 0, it will make boot error, > error log:"pll_para_config: the frequency can not be > 0 Hz". Remove them, and the lcdc driver will do the > correct clock rate setting. > > Signed-off-by: David Wu <david.wu@rock-chips.com> > --- > > Changes in v3: > - New patch > > Changes in v2: None > > arch/arm/dts/rk3288.dtsi | 7 ++----- > 1 file changed, 2 insertions(+), 5 deletions(-) > Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> The LCDC assigned rate is 0, it will make boot error, > error log:"pll_para_config: the frequency can not be > 0 Hz". Remove them, and the lcdc driver will do the > correct clock rate setting. > > Signed-off-by: David Wu <david.wu@rock-chips.com> > --- > > Changes in v3: > - New patch > > Changes in v2: None > > arch/arm/dts/rk3288.dtsi | 7 ++----- > 1 file changed, 2 insertions(+), 5 deletions(-) > Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> The LCDC assigned rate is 0, it will make boot error, > error log:"pll_para_config: the frequency can not be > 0 Hz". Remove them, and the lcdc driver will do the > correct clock rate setting. > > Signed-off-by: David Wu <david.wu@rock-chips.com> > Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> > Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> > --- > > Changes in v3: > - New patch > > Changes in v2: None > > arch/arm/dts/rk3288.dtsi | 7 ++----- > 1 file changed, 2 insertions(+), 5 deletions(-) > Applied to u-boot-rockchip, thanks!
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index da51878..2c8a616 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -604,19 +604,16 @@ u-boot,dm-pre-reloc; #clock-cells = <1>; #reset-cells = <1>; - assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, - <&cru PLL_GPLL>, <&cru PLL_CPLL>, + assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>, <&cru PLL_NPLL>, <&cru ACLK_CPU>, <&cru HCLK_CPU>, <&cru PCLK_CPU>, <&cru ACLK_PERI>, <&cru HCLK_PERI>, <&cru PCLK_PERI>; - assigned-clock-rates = <0>, <0>, - <594000000>, <400000000>, + assigned-clock-rates = <594000000>, <400000000>, <500000000>, <300000000>, <150000000>, <75000000>, <300000000>, <150000000>, <75000000>; - assigned-clock-parents = <&cru PLL_NPLL>, <&cru PLL_GPLL>; }; grf: syscon@ff770000 {
The LCDC assigned rate is 0, it will make boot error, error log:"pll_para_config: the frequency can not be 0 Hz". Remove them, and the lcdc driver will do the correct clock rate setting. Signed-off-by: David Wu <david.wu@rock-chips.com> --- Changes in v3: - New patch Changes in v2: None arch/arm/dts/rk3288.dtsi | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-)