From patchwork Sat Jan 13 06:05:12 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 860295 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3zJTfd3BHrz9t5Q for ; Sat, 13 Jan 2018 17:07:21 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0D345C21F03; Sat, 13 Jan 2018 06:06:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.6 required=5.0 tests=RCVD_IN_MSPIKE_H2, RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BDE80C21F50; Sat, 13 Jan 2018 06:05:58 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 58738C21F03; Sat, 13 Jan 2018 06:05:29 +0000 (UTC) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.138]) by lists.denx.de (Postfix) with ESMTPS id 71A8DC22242 for ; Sat, 13 Jan 2018 06:05:19 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.129]) by regular1.263xmail.com (Postfix) with ESMTP id 51E88795A; Sat, 13 Jan 2018 14:05:14 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 987B833A; Sat, 13 Jan 2018 14:05:14 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <2683cabec88e8678f0420ce2b2560c37> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 4964J8BFP6; Sat, 13 Jan 2018 14:05:15 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Sat, 13 Jan 2018 14:05:12 +0800 Message-Id: <1515823512-52858-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1515822853-52036-1-git-send-email-david.wu@rock-chips.com> References: <1515822853-52036-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, joe.hershberger@ni.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com Subject: [U-Boot] [PATCH v3 15/20] clk: rockchip: Add rk322x gamc clock support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Assuming mac_clk is fed by an external clock, set clk_rmii_src clock select control register from IO for rgmii interface. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v3: - Add "set parent" for gmac - Add internal mac clk div_sel for gmac Changes in v2: - New patch drivers/clk/rockchip/clk_rk322x.c | 107 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index c8a2413..4e6d2f0 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -239,6 +239,41 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate, return DIV_TO_RATE(src_rate, div) / 2; } +static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq) +{ + ulong ret; + + /* + * The gmac clock can be derived either from an external clock + * or can be generated from internally by a divider from SCLK_MAC. + */ + if (readl(&cru->cru_clksel_con[5]) & BIT(5)) { + /* An external clock will always generate the right rate... */ + ret = freq; + } else { + u32 con = readl(&cru->cru_clksel_con[5]); + ulong pll_rate; + u8 div; + + if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK) + pll_rate = GPLL_HZ; + else + /* CPLL is not set */ + return -EPERM; + + div = DIV_ROUND_UP(pll_rate, freq) - 1; + if (div <= 0x1f) + rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK, + div << CLK_MAC_DIV_SHIFT); + else + debug("Unsupported div for gmac:%d\n", div); + + return DIV_TO_RATE(pll_rate, div); + } + + return ret; +} + static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate, int periph, uint freq) { @@ -352,6 +387,11 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate) case CLK_DDR: new_rate = rk322x_ddr_set_clk(priv->cru, rate); break; + case SCLK_MAC: + new_rate = rk322x_mac_set_clk(priv->cru, rate); + break; + case PLL_GPLL: + return 0; default: return -ENOENT; } @@ -359,9 +399,76 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate) return new_rate; } +static int rk322x_gmac_set_parent(struct clk *clk, struct clk *parent) +{ + struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); + struct rk322x_cru *cru = priv->cru; + + /* + * If the requested parent is in the same clock-controller and the id + * is SCLK_MAC_SRC ("sclk_gmac_src"), switch to the internal clock. + */ + if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_SRC)) { + debug("%s: switching RGMII to SCLK_MAC_SRC\n", __func__); + rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0); + return 0; + } + + /* + * If the requested parent is in the same clock-controller and the id + * is SCLK_MAC_EXTCLK (sclk_mac_extclk), switch to the external clock. + */ + if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_EXTCLK)) { + debug("%s: switching RGMII to SCLK_MAC_EXTCLK\n", __func__); + rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5)); + return 0; + } + + return -EINVAL; +} + +static int rk322x_gmac_extclk_set_parent(struct clk *clk, struct clk *parent) +{ + struct rk322x_clk_priv *priv = dev_get_priv(clk->dev); + const char *clock_output_name; + struct rk322x_cru *cru = priv->cru; + int ret; + + ret = dev_read_string_index(parent->dev, "clock-output-names", + parent->id, &clock_output_name); + if (ret < 0) + return -ENODATA; + + if (!strcmp(clock_output_name, "ext_gmac")) { + debug("%s: switching gmac extclk to ext_gmac\n", __func__); + rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0); + return 0; + } else if (!strcmp(clock_output_name, "phy_50m_out")) { + debug("%s: switching gmac extclk to phy_50m_out\n", __func__); + rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10)); + return 0; + } + + return -EINVAL; +} + +static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent) +{ + switch (clk->id) { + case SCLK_MAC: + return rk322x_gmac_set_parent(clk, parent); + case SCLK_MAC_EXTCLK: + return rk322x_gmac_extclk_set_parent(clk, parent); + } + + debug("%s: unsupported clk %ld\n", __func__, clk->id); + return -ENOENT; +} + static struct clk_ops rk322x_clk_ops = { .get_rate = rk322x_clk_get_rate, .set_rate = rk322x_clk_set_rate, + .set_parent = rk322x_clk_set_parent, }; static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)