| Message ID | 1513079067-25053-1-git-send-email-faiz_abbas@ti.com |
|---|---|
| State | Accepted |
| Commit | e36edcec0a2491d1e31ddb9d82d77b9763e9aef0 |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | [U-Boot,v2] board: ti: dra7xx: Select MCAN instead of DCAN on DRA76 EVM | expand |
Hi, On Tuesday 12 December 2017 05:14 PM, Faiz Abbas wrote: > From: Vignesh R <vigneshr@ti.com> > > MCAN can be accessed via DCAN1 or DCAN2. Determining which DCAN instance > to use if any at all is done through > CTRL_CORE_CONTROL_SPARE_RW.SEL_ALT_MCAN. Since general pinmuxing is > handled in U-boot. Handle this additional pinmuxing requirement in U-boot > to ensure that MCAN is used by default via the DCAN1 pins. > > Signed-off-by: Vignesh R <vigneshr@ti.com> > [fcooper@ti.com: Update commit message and use DCAN1 not DCAN2 for MCAN] > Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> > Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> > > Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> > --- > arch/arm/include/asm/arch-omap5/mux_dra7xx.h | 3 +++ > board/ti/dra7xx/evm.c | 5 +++++ > 2 files changed, 8 insertions(+) > > diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h > index 55f49c7..dc2eb60 100644 > --- a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h > +++ b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h > @@ -351,4 +351,7 @@ > #define NMIN_DSP 0x460 > #define RSTOUTN 0x464 > > +#define MCAN_SEL_ALT_MASK 0x6000 > +#define MCAN_SEL 0x2000 > + > #endif /* _MUX_DRA7XX_H_ */ > diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c > index 6bcfa48..ddcbe31 100644 > --- a/board/ti/dra7xx/evm.c > +++ b/board/ti/dra7xx/evm.c > @@ -823,6 +823,11 @@ void recalibrate_iodelay(void) > do_set_mux32((*ctrl)->control_padconf_core_base, > delta_pads, delta_npads); > > + if (is_dra76x()) > + /* Set mux for MCAN instead of DCAN1 */ > + clrsetbits_le32((*ctrl)->control_core_control_spare_rw, > + MCAN_SEL_ALT_MASK, MCAN_SEL); > + > /* Setup IOdelay configuration */ > ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); > err: > Gentle Ping Thanks, Faiz
+ Tom On Tuesday 12 December 2017 05:14 PM, Faiz Abbas wrote: > From: Vignesh R <vigneshr@ti.com> > > MCAN can be accessed via DCAN1 or DCAN2. Determining which DCAN instance > to use if any at all is done through > CTRL_CORE_CONTROL_SPARE_RW.SEL_ALT_MCAN. Since general pinmuxing is > handled in U-boot. Handle this additional pinmuxing requirement in U-boot > to ensure that MCAN is used by default via the DCAN1 pins. Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Thanks and regards, Lokesh
On Tue, Dec 12, 2017 at 05:14:27PM +0530, Faiz Abbas wrote: > From: Vignesh R <vigneshr@ti.com> > > MCAN can be accessed via DCAN1 or DCAN2. Determining which DCAN instance > to use if any at all is done through > CTRL_CORE_CONTROL_SPARE_RW.SEL_ALT_MCAN. Since general pinmuxing is > handled in U-boot. Handle this additional pinmuxing requirement in U-boot > to ensure that MCAN is used by default via the DCAN1 pins. > > Signed-off-by: Vignesh R <vigneshr@ti.com> > [fcooper@ti.com: Update commit message and use DCAN1 not DCAN2 for MCAN] > Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> > Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> > > Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Applied to u-boot/master, thanks!
diff --git a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h index 55f49c7..dc2eb60 100644 --- a/arch/arm/include/asm/arch-omap5/mux_dra7xx.h +++ b/arch/arm/include/asm/arch-omap5/mux_dra7xx.h @@ -351,4 +351,7 @@ #define NMIN_DSP 0x460 #define RSTOUTN 0x464 +#define MCAN_SEL_ALT_MASK 0x6000 +#define MCAN_SEL 0x2000 + #endif /* _MUX_DRA7XX_H_ */ diff --git a/board/ti/dra7xx/evm.c b/board/ti/dra7xx/evm.c index 6bcfa48..ddcbe31 100644 --- a/board/ti/dra7xx/evm.c +++ b/board/ti/dra7xx/evm.c @@ -823,6 +823,11 @@ void recalibrate_iodelay(void) do_set_mux32((*ctrl)->control_padconf_core_base, delta_pads, delta_npads); + if (is_dra76x()) + /* Set mux for MCAN instead of DCAN1 */ + clrsetbits_le32((*ctrl)->control_core_control_spare_rw, + MCAN_SEL_ALT_MASK, MCAN_SEL); + /* Setup IOdelay configuration */ ret = do_set_iodelay((*ctrl)->iodelay_config_base, iodelay, niodelays); err: