From patchwork Thu Nov 9 09:26:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 836250 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yXdBp5LwRz9t5c for ; Thu, 9 Nov 2017 20:28:34 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5643FC22071; Thu, 9 Nov 2017 09:28:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: ** X-Spam-Status: No, score=3.0 required=5.0 tests=RCVD_IN_MSPIKE_BL, RCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CBEE7C22161; Thu, 9 Nov 2017 09:28:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8B174C221A6; Thu, 9 Nov 2017 09:27:05 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.135]) by lists.denx.de (Postfix) with ESMTPS id B4537C22164 for ; Thu, 9 Nov 2017 09:26:57 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.130]) by lucky1.263xmail.com (Postfix) with ESMTP id ED50E6C2E; Thu, 9 Nov 2017 17:26:53 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id C9FA83B5; Thu, 9 Nov 2017 17:26:51 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <67258df6239d163e9872606df0de0e9e> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 7795ZE0BR4; Thu, 09 Nov 2017 17:26:53 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Thu, 9 Nov 2017 17:26:12 +0800 Message-Id: <1510219572-79393-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> References: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, joe.hershberger@ni.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com Subject: [U-Boot] [PATCH v2 15/18] rockchip: pinctrl: Add rk322x gmac pinctrl support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Set gmac pins iomux and rgmii tx pins to 12ma drive-strength, clean others to 2ma. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: - New patch drivers/pinctrl/rockchip/pinctrl_rk322x.c | 138 ++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/drivers/pinctrl/rockchip/pinctrl_rk322x.c b/drivers/pinctrl/rockchip/pinctrl_rk322x.c index 28d9996..956e02f 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk322x.c @@ -470,6 +470,48 @@ enum { CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT, }; +/* GRF_GPIO2B_E */ +enum { + GRF_GPIO2B0_E_SHIFT = 0, + GRF_GPIO2B0_E_MASK = GENMASK(1, 0), + GRF_GPIO2B1_E_SHIFT = 2, + GRF_GPIO2B1_E_MASK = GENMASK(3, 2), + GRF_GPIO2B3_E_SHIFT = 6, + GRF_GPIO2B3_E_MASK = GENMASK(7, 6), + GRF_GPIO2B4_E_SHIFT = 8, + GRF_GPIO2B4_E_MASK = GENMASK(9, 8), + GRF_GPIO2B5_E_SHIFT = 10, + GRF_GPIO2B5_E_MASK = GENMASK(11, 10), + GRF_GPIO2B6_E_SHIFT = 12, + GRF_GPIO2B6_E_MASK = GENMASK(13, 12), +}; + +/* GRF_GPIO2C_E */ +enum { + GRF_GPIO2C0_E_SHIFT = 0, + GRF_GPIO2C0_E_MASK = GENMASK(1, 0), + GRF_GPIO2C1_E_SHIFT = 2, + GRF_GPIO2C1_E_MASK = GENMASK(3, 2), + GRF_GPIO2C2_E_SHIFT = 4, + GRF_GPIO2C2_E_MASK = GENMASK(5, 4), + GRF_GPIO2C3_E_SHIFT = 6, + GRF_GPIO2C3_E_MASK = GENMASK(7, 6), + GRF_GPIO2C4_E_SHIFT = 8, + GRF_GPIO2C4_E_MASK = GENMASK(9, 8), + GRF_GPIO2C5_E_SHIFT = 10, + GRF_GPIO2C5_E_MASK = GENMASK(11, 10), + GRF_GPIO2C6_E_SHIFT = 12, + GRF_GPIO2C6_E_MASK = GENMASK(13, 12), + GRF_GPIO2C7_E_SHIFT = 14, + GRF_GPIO2C7_E_MASK = GENMASK(15, 14), +}; + +/* GRF_GPIO2D_E */ +enum { + GRF_GPIO2D1_E_SHIFT = 2, + GRF_GPIO2D1_E_MASK = GENMASK(3, 2), +}; + struct rk322x_pinctrl_priv { struct rk322x_grf *grf; }; @@ -633,6 +675,95 @@ static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id) } } +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) +static void pinctrl_rk322x_gmac_config(struct rk322x_grf *grf, int gmac_id) +{ + switch (gmac_id) { + case PERIPH_ID_GMAC: + /* set rgmii pins mux */ + rk_clrsetreg(&grf->gpio2b_iomux, + GPIO2B0_MASK | + GPIO2B1_MASK | + GPIO2B3_MASK | + GPIO2B4_MASK | + GPIO2B5_MASK | + GPIO2B6_MASK, + GPIO2B0_GMAC_RXDV << GPIO2B0_SHIFT | + GPIO2B1_GMAC_TXCLK << GPIO2B1_SHIFT | + GPIO2B3_GMAC_RXCLK << GPIO2B3_SHIFT | + GPIO2B4_GMAC_MDIO << GPIO2B4_SHIFT | + GPIO2B5_GMAC_TXEN << GPIO2B5_SHIFT | + GPIO2B6_GMAC_CLK << GPIO2B6_SHIFT); + + rk_clrsetreg(&grf->gpio2c_iomux, + GPIO2C0_MASK | + GPIO2C1_MASK | + GPIO2C2_MASK | + GPIO2C3_MASK | + GPIO2C4_MASK | + GPIO2C5_MASK | + GPIO2C6_MASK | + GPIO2C7_MASK, + GPIO2C0_GMAC_RXD1 << GPIO2C0_SHIFT | + GPIO2C1_GMAC_RXD0 << GPIO2C1_SHIFT | + GPIO2C2_GMAC_TXD1 << GPIO2C2_SHIFT | + GPIO2C3_GMAC_TXD0 << GPIO2C3_SHIFT | + GPIO2C4_GMAC_RXD3 << GPIO2C4_SHIFT | + GPIO2C5_GMAC_RXD2 << GPIO2C5_SHIFT | + GPIO2C6_GMAC_TXD2 << GPIO2C6_SHIFT | + GPIO2C7_GMAC_TXD3 << GPIO2C7_SHIFT); + + rk_clrsetreg(&grf->gpio2d_iomux, + GPIO2D1_MASK, + GPIO2D1_GMAC_MDC << GPIO2D1_SHIFT); + + /* + * set rgmii tx pins to 12ma drive-strength, + * clean others with 2ma. + */ + rk_clrsetreg(&grf->gpio2_e[1], + GRF_GPIO2B0_E_MASK | + GRF_GPIO2B1_E_MASK | + GRF_GPIO2B3_E_MASK | + GRF_GPIO2B4_E_MASK | + GRF_GPIO2B5_E_MASK | + GRF_GPIO2B6_E_MASK, + 0x0 << GRF_GPIO2B0_E_SHIFT | + 0x3 << GRF_GPIO2B1_E_SHIFT | + 0x0 << GRF_GPIO2B3_E_SHIFT | + 0x0 << GRF_GPIO2B4_E_SHIFT | + 0x3 << GRF_GPIO2B5_E_SHIFT | + 0x0 << GRF_GPIO2B6_E_SHIFT); + + rk_clrsetreg(&grf->gpio2_e[2], + GRF_GPIO2C0_E_MASK | + GRF_GPIO2C1_E_MASK | + GRF_GPIO2C2_E_MASK | + GRF_GPIO2C3_E_MASK | + GRF_GPIO2C4_E_MASK | + GRF_GPIO2C5_E_MASK | + GRF_GPIO2C6_E_MASK | + GRF_GPIO2C7_E_MASK, + 0x0 << GRF_GPIO2C0_E_SHIFT | + 0x0 << GRF_GPIO2C1_E_SHIFT | + 0x3 << GRF_GPIO2C2_E_SHIFT | + 0x3 << GRF_GPIO2C3_E_SHIFT | + 0x0 << GRF_GPIO2C4_E_SHIFT | + 0x0 << GRF_GPIO2C5_E_SHIFT | + 0x3 << GRF_GPIO2C6_E_SHIFT | + 0x3 << GRF_GPIO2C7_E_SHIFT); + + rk_clrsetreg(&grf->gpio2_e[3], + GRF_GPIO2D1_E_MASK, + 0x0 << GRF_GPIO2D1_E_SHIFT); + break; + default: + debug("gmac id = %d iomux error!\n", gmac_id); + break; + } +} +#endif + static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags) { struct rk322x_pinctrl_priv *priv = dev_get_priv(dev); @@ -662,6 +793,9 @@ static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags) case PERIPH_ID_SDMMC1: pinctrl_rk322x_sdmmc_config(priv->grf, func); break; + case PERIPH_ID_GMAC: + pinctrl_rk322x_gmac_config(priv->grf, func); + break; default: return -EINVAL; } @@ -701,6 +835,10 @@ static int rk322x_pinctrl_get_periph_id(struct udevice *dev, return PERIPH_ID_UART1; case 57: return PERIPH_ID_UART2; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) + case 24: + return PERIPH_ID_GMAC; +#endif } return -ENOENT; }