From patchwork Thu Nov 9 09:02:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 836232 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yXcfK5kqdz9t5Q for ; Thu, 9 Nov 2017 20:03:53 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 31E95C21FCD; Thu, 9 Nov 2017 09:03:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: ** X-Spam-Status: No, score=3.0 required=5.0 tests=RCVD_IN_MSPIKE_BL, RCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6DADFC21F5F; Thu, 9 Nov 2017 09:03:21 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id EFB7FC21F5D; Thu, 9 Nov 2017 09:03:18 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.131]) by lists.denx.de (Postfix) with ESMTPS id 57DEBC21F5F for ; Thu, 9 Nov 2017 09:03:18 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.234]) by lucky1.263xmail.com (Postfix) with ESMTP id 7ABC396F16; Thu, 9 Nov 2017 17:03:14 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id A01643C6; Thu, 9 Nov 2017 17:03:12 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 16622ODYWXD; Thu, 09 Nov 2017 17:03:14 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Thu, 9 Nov 2017 17:02:29 +0800 Message-Id: <1510218149-78706-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> References: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, joe.hershberger@ni.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com Subject: [U-Boot] [PATCH v2 06/18] net: gmac_rockchip: Add support for the RV1108 GMAC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The rv1108 GMAC only support rmii interface, so need to add the set_rmii() ops. Use the phy current interface to set rmii or rgmii ops. At the same time, need to set the mac clock rate of rmii with 50M, the clock rate of rgmii with 125M. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: - Add check whether the set rgmii/rmii function is a valid function pointer - Use current phy interface to set mac clock rate - Clean the grf offset at gmac_rockchip.c drivers/net/gmac_rockchip.c | 89 +++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 82 insertions(+), 7 deletions(-) diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 586ccbf..22e3941 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include "designware.h" @@ -37,6 +38,7 @@ struct gmac_rockchip_platdata { struct rk_gmac_ops { int (*fix_mac_speed)(struct dw_eth_dev *priv); + void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); }; @@ -142,6 +144,41 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; } +static int rv1108_set_rmii_speed(struct dw_eth_dev *priv) +{ + struct rv1108_grf *grf; + int clk, speed; + enum { + RV1108_GMAC_SPEED_MASK = BIT(2), + RV1108_GMAC_SPEED_10M = 0 << 2, + RV1108_GMAC_SPEED_100M = 1 << 2, + RV1108_GMAC_CLK_SEL_MASK = BIT(7), + RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, + RV1108_GMAC_CLK_SEL_25M = 1 << 7, + }; + + switch (priv->phydev->speed) { + case 10: + clk = RV1108_GMAC_CLK_SEL_2_5M; + speed = RV1108_GMAC_SPEED_10M; + break; + case 100: + clk = RV1108_GMAC_CLK_SEL_25M; + speed = RV1108_GMAC_SPEED_100M; + break; + default: + debug("Unknown phy speed: %d\n", priv->phydev->speed); + return -EINVAL; + } + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->gmac_con0, + RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, + clk | speed); + + return 0; +} + static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) { struct rk3288_grf *grf; @@ -221,11 +258,28 @@ static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); } +static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) +{ + struct rv1108_grf *grf; + + enum { + RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), + RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, + }; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->gmac_con0, + RV1108_GMAC_PHY_INTF_SEL_MASK, + RV1108_GMAC_PHY_INTF_SEL_RMII); +} + static int gmac_rockchip_probe(struct udevice *dev) { struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); struct rk_gmac_ops *ops = (struct rk_gmac_ops *)dev_get_driver_data(dev); + struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); + struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata; struct clk clk; int ret; @@ -233,13 +287,27 @@ static int gmac_rockchip_probe(struct udevice *dev) if (ret) return ret; - /* Since mac_clk is fed by an external clock we can use 0 here */ - ret = clk_set_rate(&clk, 0); - if (ret) - return ret; - - /* Set to RGMII mode */ - ops->set_to_rgmii(pdata); + switch (eth_pdata->phy_interface) { + case PHY_INTERFACE_MODE_RGMII: + ret = clk_set_rate(&clk, 125000000); + if (IS_ERR_VALUE(ret)) + return ret; + /* Set to RGMII mode */ + if (ops->set_to_rgmii) + ops->set_to_rgmii(pdata); + break; + case PHY_INTERFACE_MODE_RMII: + ret = clk_set_rate(&clk, 50000000); + if (IS_ERR_VALUE(ret)) + return ret; + /* Set to RMII mode */ + if (ops->set_to_rmii) + ops->set_to_rmii(pdata); + break; + default: + debug("NO interface defined!\n"); + return -ENXIO; + } return designware_eth_probe(dev); } @@ -289,6 +357,11 @@ const struct rk_gmac_ops rk3399_gmac_ops = { .set_to_rgmii = rk3399_gmac_set_to_rgmii, }; +const struct rk_gmac_ops rv1108_gmac_ops = { + .fix_mac_speed = rv1108_set_rmii_speed, + .set_to_rmii = rv1108_gmac_set_to_rmii, +}; + static const struct udevice_id rockchip_gmac_ids[] = { { .compatible = "rockchip,rk3288-gmac", .data = (ulong)&rk3288_gmac_ops }, @@ -296,6 +369,8 @@ static const struct udevice_id rockchip_gmac_ids[] = { .data = (ulong)&rk3368_gmac_ops }, { .compatible = "rockchip,rk3399-gmac", .data = (ulong)&rk3399_gmac_ops }, + { .compatible = "rockchip,rv1108-gmac", + .data = (ulong)&rv1108_gmac_ops }, { } };